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Static timing analysis
Known as:
Slow model analysis
, Fast model analysis
, STA
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Static timing analysis (STA) is a simulation method of computing the expected timing of a digital circuit without requiring a simulation of the full…
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Related topics
Related topics
38 relations
Application-specific integrated circuit
Circuit extraction
Clock signal
Clock skew
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Broader (1)
Formal methods
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2014
Highly Cited
2014
Bus designs for time-probabilistic multicore processors
J. Jalle
,
Leonidas Kosmidis
,
J. Abella
,
Eduardo Quiñones
,
F. Cazorla
Design, Automation and Test in Europe
2014
Corpus ID: 9687950
Probabilistic Timing Analysis (PTA) reduces the amount of information needed to provide tight WCET estimates in real-time systems…
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Highly Cited
2014
Highly Cited
2014
A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems
Yogen Krish
,
Z. Wu
,
R. Pellizzoni
Euromicro Conference on Real-Time Systems
2014
Corpus ID: 7126629
We introduce ROC, a Rank-switching, Open-row Controller for Double Data Rate Dynamic RAM (DDR DRAM). ROC is optimized for mixed…
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Highly Cited
2009
Highly Cited
2009
Variable-latency design by function speculation
David Bañeres
,
J. Cortadella
,
M. Kishinevsky
Design, Automation & Test in Europe Conference…
2009
Corpus ID: 14991747
Variable-latency designs may improve the performance of those circuits in which the worst-case delay paths are infrequently…
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2006
2006
Voltage-Aware Static Timing Analysis
D. Kouroussis
,
Rubil Ahmadi
,
F. Najm
IEEE Transactions on Computer-Aided Design of…
2006
Corpus ID: 8516060
Static timing analysis (STA) techniques allow a designer to check the timing of a circuit at different process corners, which…
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2005
2005
Static timing analysis considering power supply variations
Sanjay Pant
,
D. Blaauw
ICCAD. IEEE/ACM International Conference on…
2005
Corpus ID: 51891310
Power supply integrity verification has become a key concern in high performance designs. In deep submicron technologies, power…
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2004
2004
Static timing analysis using backward signal propagation
Dongwook Lee
,
V. Zolotov
,
D. Blaauw
Proceedings - Design Automation Conference
2004
Corpus ID: 239965
In this paper, we address the problem of signal pruning in static timing analysis (STA). Traditionally, signals are propagated…
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Highly Cited
2002
Highly Cited
2002
FPGA Realization of Wavelet Transform for Detection of Electric Power System Disturbances
Shyh-Jier Huang
,
Tsai-Ming Yang
,
Jiann-Tseng Huang
IEEE Power Engineering Review
2002
Corpus ID: 35514049
Realization of wavelet transform on field-programmable gate array (FPGA) devices for the detection of power system disturbances…
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Highly Cited
2002
Highly Cited
2002
Embedded timing analysis: a soc infrastructure
S. Tabatabaei
,
A. Ivanov
IEEE Design & Test of Computers
2002
Corpus ID: 23219114
This SoC infrastructure core is a flexible, scalable, and highly accurate embedded time interval analyzer (ETIA), used to measure…
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Highly Cited
1992
Highly Cited
1992
Certified timing verification and the transition delay of a logic circuit
S. Devadas
,
K. Keutzer
,
S. Malik
,
Albert R. Wang
[] Proceedings 29th ACM/IEEE Design Automation…
1992
Corpus ID: 14425007
The transition delay of a circuit is examined. It is shown that the transition delay of a circuit can differ from the floating…
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Highly Cited
1990
Highly Cited
1990
CheckT/sub c/ and minT/sub c/: timing verification and optimal clocking of synchronous digital circuits
K. Sakallah
,
T. Mudge
,
K. Olukotun
IEEE International Conference on Computer-Aided…
1990
Corpus ID: 12958767
Two CAD tools, checkT/sub c/ and minT/sub c/, for timing verification and optimal clocking are introduced. Both tools are based…
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