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Static timing analysis

Known as: Slow model analysis, Fast model analysis, STA 
Static timing analysis (STA) is a simulation method of computing the expected timing of a digital circuit without requiring a simulation of the full… 
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Related topics

Related topics

38 relations
Application-specific integrated circuitCircuit extractionClock signalClock skew

Broader (1)

Formal methods

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2014
Highly Cited
2014
Bus designs for time-probabilistic multicore processors
Probabilistic Timing Analysis (PTA) reduces the amount of information needed to provide tight WCET estimates in real-time systems… 
Highly Cited
2010
Highly Cited
2010
ANALYSIS OF KEPLER'S SHORT-CADENCE PHOTOMETRY FOR TrES-2b
We present an analysis of 18 short-cadence (SC) transit light curves of TrES-2b using quarter 0 (Q0) and quarter 1 (Q1) from the… 
Highly Cited
2009
Highly Cited
2009
Variable-latency design by function speculation
Variable-latency designs may improve the performance of those circuits in which the worst-case delay paths are infrequently… 
2006
2006
Voltage-Aware Static Timing Analysis
Static timing analysis (STA) techniques allow a designer to check the timing of a circuit at different process corners, which… 
2004
2004
Static timing analysis using backward signal propagation
In this paper, we address the problem of signal pruning in static timing analysis (STA). Traditionally, signals are propagated… 
Highly Cited
2002
Highly Cited
2002
Embedded timing analysis: a soc infrastructure
This SoC infrastructure core is a flexible, scalable, and highly accurate embedded time interval analyzer (ETIA), used to measure… 
Highly Cited
1992
Highly Cited
1992
Certified timing verification and the transition delay of a logic circuit
The transition delay of a circuit is examined. It is shown that the transition delay of a circuit can differ from the floating… 
1991
1991
Static timing analysis using interval constraints
The authors have reduced the uncertainty inherent in timing analysis due to lack of proper signal interaction modeling and delay… 
Highly Cited
1990
Highly Cited
1990
CheckT/sub c/ and minT/sub c/: timing verification and optimal clocking of synchronous digital circuits
Two CAD tools, checkT/sub c/ and minT/sub c/, for timing verification and optimal clocking are introduced. Both tools are based… 
1986
1986
An accuration delay modeling technique for switch-level timing verification
A new delay modeling technique for accurate timing verification of digital MOS circuits is presented. The technique is based on… 
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