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Static timing analysis
Known as:
Slow model analysis
, Fast model analysis
, STA
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Static timing analysis (STA) is a simulation method of computing the expected timing of a digital circuit without requiring a simulation of the full…
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Related topics
Related topics
38 relations
Application-specific integrated circuit
Circuit extraction
Clock signal
Clock skew
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Broader (1)
Formal methods
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2012
2012
Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs
Xiaoxia Wu
,
Wei Zhao
,
+6 authors
Yuan Xie
IEEE Transactions on Very Large Scale Integration…
2012
Corpus ID: 9540246
Reducing interconnect delay and power consumption has become a major concern in deep submicron designs. 3-D technologies have…
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2008
2008
Achieving Industrial Strength Timing Predictions of Embedded System Behavior
Mikael Nolin
,
Jukka Mäki-Turja
,
Kaj Hänninen
Embedded Systems and Applications
2008
Corpus ID: 17999672
This paper discusses why the extensive scientific results on predicting embedded systems temporal behavior never, or very seldom…
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2006
2006
NoC Monitoring Hardware Support for Fast NoC Design Space Exploration and Potential NoC Partial Dynamic Reconfiguration
Riad Ben Mouhoub
,
O. Hammami
International Symposium on Industrial Embedded…
2006
Corpus ID: 1542433
The Multiprocessor systems on chip are strongly emerging in various embedded systems to support dramatic growth of complex…
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2005
2005
AES side channel attack protection using random isomorphisms.
A. Rostovtsev
,
O. Shemyakina
2005
Corpus ID: 5539709
General method of side-channel attacks protection, based on random cipher isomorphisms is presented. Isomorphic ciphers produce…
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2000
2000
VLSI system design using asynchronous wave pipelines: a 0.35 /spl mu/m CMOS 1.5 GHz elliptic curve public key cryptosystem chip
O. Hauck
,
A. Katoch
,
S. Huss
Symposium on Asynchronous Circuits and Systems
2000
Corpus ID: 6394793
This paper presents VLSI system design using asynchronous wave pipelines (AWPs) with a public key crypto chip as an example. The…
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2000
2000
Primitive path delay faults: identification and their use in timinganalysis
M. Sivaraman
,
A. Strojwas
IEEE Trans. Comput. Aided Des. Integr. Circuits…
2000
Corpus ID: 20595455
Present-day digital systems are characterized by large complexity, operation under tight timing constraints, numerous false paths…
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1994
1994
Predicting circuit performance using circuit-level statistical timing analysis
R. B. Brawhear
,
N. Menezes
,
C. Oh
,
L. T. Pillage
,
M. R. Mercer
Proceedings of European Design and Test…
1994
Corpus ID: 32006065
Recognizing that the delay of a circuit is extremely sensitive to manufacturing process variations, this paper proposes a…
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1992
1992
On the stability of moment-matching approximations in asymptotic waveform evaluation
D. F. Anastasakis
,
N. Gopal
,
Seok-Yoon Kim
,
L. T. Pillage
[] Proceedings 29th ACM/IEEE Design Automation…
1992
Corpus ID: 15499821
Asymptotic waveform evaluation (AWE), which is based upon moment-matching, has been demonstrated as an efficient approach for CAD…
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1991
1991
Static timing analysis using interval constraints
Ronald B. Stewart
,
J. Benkoski
IEEE International Conference on Computer-Aided…
1991
Corpus ID: 32720436
The authors have reduced the uncertainty inherent in timing analysis due to lack of proper signal interaction modeling and delay…
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1987
1987
A New Approach to Hierarchical and Statistical Timing Simulations
J. Benkoski
,
A. Strojwas
IEEE Transactions on Computer-Aided Design of…
1987
Corpus ID: 15304426
This paper describes a new approach for timing analysis in general and, more specifically, for statistical timing analysis. A…
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