Static timing analysis

Known as: Slow model analysis, Fast model analysis, STA

Static timing analysis (STA) is a simulation method of computing the expected timing of a digital circuit without requiring a simulation of the full…

Papers overview

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2012

Reducing interconnect delay and power consumption has become a major concern in deep submicron designs. 3-D technologies have…

2006

Static timing analysis (STA) techniques allow a designer to check the timing of a circuit at different process corners, which…

2005

A comprehensive probabilistic methodology is proposed to solve the buffer insertion problem with the consideration of process…

2003

Increasing delay variation due to capacitive and inductive crosstalk has a dramatic impact on deep submicron technologies. It is…

2003

A novel low power multiplication algorithm for reducing switching activity through operand decomposition is proposed. Our…

2000

This paper presents VLSI system design using asynchronous wave pipelines (AWPs) with a public key crypto chip as an example. The…

1999

Modern high-performance asynchronous circuits depend on timing constraints for correct operation, so timing analyzers are…

1994

Recognizing that the delay of a circuit is extremely sensitive to manufacturing process variations, this paper proposes a…

1992

Asymptotic waveform evaluation (AWE), which is based upon moment-matching, has been demonstrated as an efficient approach for CAD…

1976

There are many activities included under the category of design automation for integrated circuits. Some of these activities…