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Static timing analysis

Known as: Slow model analysis, Fast model analysis, STA 
Static timing analysis (STA) is a simulation method of computing the expected timing of a digital circuit without requiring a simulation of the full… 
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Papers overview

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2012
2012
Reducing interconnect delay and power consumption has become a major concern in deep submicron designs. 3-D technologies have… 
2008
2008
This paper discusses why the extensive scientific results on predicting embedded systems temporal behavior never, or very seldom… 
2006
2006
The Multiprocessor systems on chip are strongly emerging in various embedded systems to support dramatic growth of complex… 
2005
2005
General method of side-channel attacks protection, based on random cipher isomorphisms is presented. Isomorphic ciphers produce… 
2000
2000
This paper presents VLSI system design using asynchronous wave pipelines (AWPs) with a public key crypto chip as an example. The… 
2000
2000
Present-day digital systems are characterized by large complexity, operation under tight timing constraints, numerous false paths… 
1994
1994
Recognizing that the delay of a circuit is extremely sensitive to manufacturing process variations, this paper proposes a… 
1992
1992
  • D. F. AnastasakisN. GopalSeok-Yoon KimL. T. Pillage
  • 1992
  • Corpus ID: 15499821
Asymptotic waveform evaluation (AWE), which is based upon moment-matching, has been demonstrated as an efficient approach for CAD… 
1991
1991
The authors have reduced the uncertainty inherent in timing analysis due to lack of proper signal interaction modeling and delay… 
1987
1987
This paper describes a new approach for timing analysis in general and, more specifically, for statistical timing analysis. A…