T. Mudge

Publications
Influence

MiBench: A free, commercially representative embedded benchmark suite

M. Guthaus, J. Ringenberg, Dan Ernst, T. Austin, T. Mudge, R. Brown
Computer Science
2 December 2001

This paper examines a set of commercially representative embedded programs and compares them to an existing benchmark suite, SPEC2000. Expand

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Razor: a low-power pipeline based on circuit-level timing speculation

Dan Ernst, Nam Sung Kim, +8 authors T. Mudge
Computer Science
Proceedings. 36th Annual IEEE/ACM International…
3 December 2003

In this paper, we propose a new approach to DVS, called Razor, based on dynamic detection and correction of circuit timing errors. Expand

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation

Dan Ernst, Nam Sung Kim, +8 authors T. Mudge
Computer Science
MICRO
2003

We propose a solution by which the circuit can be operated even below the ‘critical’ voltage, so that no margins are required and thus more energy can be saved. Expand

Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits

Ronald G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, T. Mudge
Engineering, Computer Science
Proceedings of the IEEE
22 January 2010

This paper defines and explores near-threshold computing, a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. Expand

Drowsy caches: simple techniques for reducing leakage power

K. Flautner, Nam Sung Kim, S. Martin, D. Blaauw, T. Mudge
Proceedings 29th Annual International Symposium…
2002

On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power… Expand

Leakage Current: Moore's Law Meets Static Power

Nam Sung Kim, T. Austin, +6 authors N. Vijaykrishnan
Computer Science
Computer
1 December 2003

Off-state leakage is static power, current that leaks through transistors even when they are turned off. Expand

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47
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Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads

S. M. Martin, K. Flautner, T. Mudge, D. Blaauw
Engineering
ICCAD
10 November 2002

In this paper, we show how the simultaneous use of adaptive body biasing (ABB) and DVS can be used to reduce power in high-performance processors. Expand

Neurosurgeon: Collaborative Intelligence Between the Cloud and Mobile Edge

Yiping Kang, Johann Hauswald, +4 authors L. Tang
Computer Science
ASPLOS
4 April 2017

The computation for today's intelligent personal assistants such as Apple Siri, Google Now, and Microsoft Cortana, is performed in the cloud. Expand

A self-tuning DVS processor using delay-error detection and correction

S. Das, S. Pant, +5 authors K. Flautner
Computer Science
VLSIC
16 June 2005

In this paper, we present the implementation and silicon measurements results of a 64bit processor fabricated in 0.18/spl mu/m technology. Expand

Drowsy caches: simple techniques for reducing leakage power

K. Flautner, Nam Sung Kim, S. M. Martin, D. Blaauw, T. Mudge
Computer Science
ISCA
25 May 2002

We show that with simple architectural techniques, about 80%-90% of the cache lines can be maintained in a drowsy state without affecting performance by more than 1%. Expand

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