MiBench: A free, commercially representative embedded benchmark suite
- M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, R.B. Brown
- Computer ScienceProceedings of the Fourth Annual IEEE…
- 2 December 2001
A new version of SimpleScalar that has been adapted to the ARM instruction set is used to characterize the performance of the benchmarks using configurations similar to current and next generation embedded processors.
Razor: a low-power pipeline based on circuit-level timing speculation
- D. Ernst, N. Kim, T. Mudge
- EngineeringProceedings. 36th Annual IEEE/ACM International…
- 3 December 2003
A solution by which the circuit can be operated even below the ‘critical’ voltage, so that no margins are required and thus more energy can be saved.
Neurosurgeon: Collaborative Intelligence Between the Cloud and Mobile Edge
- Yiping Kang, Johann Hauswald, Lingjia Tang
- Computer ScienceInternational Conference on Architectural Support…
- 4 April 2017
Neurosurgeon, a lightweight scheduler to automatically partition DNN computation between mobile devices and datacenters at the granularity of neural network layers is designed, finding that a fine-grained, layer-level computation partitioning strategy based on the data and computation variations of each layer within a DNN has significant latency and energy advantages over the status quo approach.
Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits
- R. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, T. Mudge
- Computer ScienceProceedings of the IEEE
- 22 January 2010
The barriers to the widespread adoption of near-threshold computing are explored and current work aimed at overcoming these obstacles are described.
Drowsy caches: simple techniques for reducing leakage power
- K. Flautner, N. Kim, Steven M. Martin, D. Blaauw, T. Mudge
- Computer ScienceProceedings 29th Annual International Symposium…
- 25 May 2002
It is argued that the use of drowsy caches can simplify the design and control of low-leakage caches, and avoid the need to completely turn off selected cache lines and lose their state.
A self-tuning DVS processor using delay-error detection and correction
A dynamic voltage scaling (DVS) technique called Razor is presented which incorporates an in situ error detection and correction mechanism to recover from timing errors and achieves an average energy savings of 50% over worst case operating conditions.
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
- Steven M. Martin, K. Flautner, T. Mudge, D. Blaauw
- EngineeringIEEE/ACM International Conference on Computer…
- 10 November 2002
Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power saving by DVS alone is becoming limited as leakage power…
Leakage Current: Moore's Law Meets Static Power
Off-state leakage is static power, current that leaks through transistors even when they are turned off. The other source of power dissipation in today's microprocessors, dynamic power, arises from…
The YAGS branch prediction scheme
YAGS introduces tags into the PHT that allows it to be reduced without sacrificing key branch outcome information, and shows that YAGS gives better prediction accuracy for the SPEC95 benchmark suite than several leading prediction schemes, for the same cost.
The bi-mode branch predictor
- Chih-Chieh Lee, I-Cheng K. Chen, T. Mudge
- Computer ScienceProceedings of 30th Annual International…
- 1 December 1997
A new dynamic predictor is proposed, the bi mode predictor, which divides the prediction tables into two halves and by dynamically determining the current "mode" of the program, selects the appropriate half of the table for prediction.