• Publications
  • Influence
MiBench: A free, commercially representative embedded benchmark suite
TLDR
This paper examines a set of commercially representative embedded programs and compares them to an existing benchmark suite, SPEC2000. Expand
  • 3,437
  • 397
  • PDF
Razor: a low-power pipeline based on circuit-level timing speculation
TLDR
In this paper, we propose a new approach to DVS, called Razor, based on dynamic detection and correction of circuit timing errors. Expand
  • 887
  • 154
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
TLDR
We propose a solution by which the circuit can be operated even below the ‘critical’ voltage, so that no margins are required and thus more energy can be saved. Expand
  • 512
  • 68
  • PDF
Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits
TLDR
This paper defines and explores near-threshold computing, a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. Expand
  • 731
  • 67
  • PDF
Drowsy caches: simple techniques for reducing leakage power
On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase powerExpand
  • 377
  • 66
  • PDF
Leakage Current: Moore's Law Meets Static Power
TLDR
Off-state leakage is static power, current that leaks through transistors even when they are turned off. Expand
  • 1,169
  • 47
  • PDF
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
TLDR
In this paper, we show how the simultaneous use of adaptive body biasing (ABB) and DVS can be used to reduce power in high-performance processors. Expand
  • 492
  • 46
  • PDF
Neurosurgeon: Collaborative Intelligence Between the Cloud and Mobile Edge
TLDR
The computation for today's intelligent personal assistants such as Apple Siri, Google Now, and Microsoft Cortana, is performed in the cloud. Expand
  • 291
  • 46
  • PDF
A self-tuning DVS processor using delay-error detection and correction
TLDR
In this paper, we present the implementation and silicon measurements results of a 64bit processor fabricated in 0.18/spl mu/m technology. Expand
  • 225
  • 43
Drowsy caches: simple techniques for reducing leakage power
TLDR
We show that with simple architectural techniques, about 80%-90% of the cache lines can be maintained in a drowsy state without affecting performance by more than 1%. Expand
  • 529
  • 31
  • PDF