• Publications
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MiBench: A free, commercially representative embedded benchmark suite
A new version of SimpleScalar that has been adapted to the ARM instruction set is used to characterize the performance of the benchmarks using configurations similar to current and next generation embedded processors. Expand
Razor: a low-power pipeline based on circuit-level timing speculation
  • D. Ernst, N. Kim, +8 authors T. Mudge
  • Computer Science
  • Proceedings. 36th Annual IEEE/ACM International…
  • 3 December 2003
A new approach to DVS is proposed, called Razor, based on dynamic detection and correction of circuit timing errors, to tune the supply voltage by monitoring the error rate during circuit operation, thereby eliminating the need for voltage margins and exploiting the data dependence of circuit delay. Expand
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
A solution by which the circuit can be operated even below the ‘critical’ voltage, so that no margins are required and thus more energy can be saved. Expand
Neurosurgeon: Collaborative Intelligence Between the Cloud and Mobile Edge
Neurosurgeon, a lightweight scheduler to automatically partition DNN computation between mobile devices and datacenters at the granularity of neural network layers is designed, finding that a fine-grained, layer-level computation partitioning strategy based on the data and computation variations of each layer within a DNN has significant latency and energy advantages over the status quo approach. Expand
Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits
The barriers to the widespread adoption of near-threshold computing are explored and current work aimed at overcoming these obstacles are described. Expand
Drowsy caches: simple techniques for reducing leakage power
On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase powerExpand
Leakage Current: Moore's Law Meets Static Power
Off-state leakage is static power, current that leaks through transistors even when they are turned off. The other source of power dissipation in today's microprocessors, dynamic power, arises fromExpand
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power savings by DVS alone is becoming limited as leakage powerExpand
A self-tuning DVS processor using delay-error detection and correction
A 64bit processor fabricated in 0.18/spl mu/m technology employs delay-error detection and correction scheme called Razor to eliminate voltage safety margins and scale voltage 120mV below the first failure point to achieve 44% energy savings over the worst case operating conditions. Expand
Drowsy caches: simple techniques for reducing leakage power
It is argued that the use of drowsy caches can simplify the design and control of low-leakage caches, and avoid the need to completely turn off selected cache lines and lose their state. Expand