David Bañeres

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Variable-latency designs may improve the performance of those circuits in which the worst-case delay paths are infrequently activated. <i>Telescopic units</i> emerged as a scheme to automatically synthesize variable-latency circuits. In this paper, a novel approach is proposed that brings three main contributions with regard to the methods used for(More)
In this paper we analyze three well-known preprocessors for Max-SAT. The first pre-processor is based on the so-called variable saturation. The second preprocessor is based on the resolution mechanism incorporated in modern branch and bound solvers. The third preprocessor is specific for the Maximum Clique problem and other problems with similar encoding in(More)
An approach for layout-aware interconnect optimization is presented. It is based on the combination of three sub-problems into the same framework: gate duplication, buffer insertion and placement. Different techniques to control the combinatorial explosion are proposed. The experimental results show tangible benefits in delay that endorse the suitability(More)