David Bañeres

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Variable-latency designs may improve the performance of those circuits in which the worst-case delay paths are infrequently activated. <i>Telescopic units</i> emerged as a scheme to automatically synthesize variable-latency circuits. In this paper, a novel approach is proposed that brings three main contributions with regard to the methods used for(More)
In this paper we analyze three well-known preprocessors for Max-SAT. The first pre-processor is based on the so-called variable saturation. The second preprocessor is based on the resolution mechanism incorporated in modern branch and bound solvers. The third preprocessor is specific for the Maximum Clique problem and other problems with similar encoding in(More)
An approach for layout-aware interconnect optimization is presented. It is based on the combination of three sub-problems into the same framework: gate duplication, buffer insertion and placement. Different techniques to control the combinatorial explosion are proposed. The experimental results show tangible benefits in delay that endorse the suitability(More)
Logic decomposition has been extensively used to optimize the worst-case delay and the area in the technology independent phase. Bi-decomposition is one of the state-of-art techniques to reduce the depth of the netlist due to the affordable computational cost. We present a novel n-way decomposition technique that improves bi-decomposition. The problem of(More)
—Current placement algorithms aim at routable layouts with shortest wirelength and mostly minimize the total Half-Perimeter Wirelength (HPWL) of nets. A new clustering net model is proposed for better handling of high degree hyperedges, for which the HPWL can significantly underestimate wirelength. Splitting a net into several lower degree subnets, the(More)
Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techniques are not always suitable for delay and area logic optimizations. The paper presents an approach that uses a dominator-based partitioning and conventional logic synthesis(More)