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An Analyzable Memory Controller for Hard Real-Time CMPs
Multicore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation forExpand
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Dynamically Controlled Resource Allocation in SMT Processors
SMT processors increase performance by executing instructions from several threads simultaneously. These threads use the resources of the processor better by sharing them but, at the same time,Expand
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Measurement-Based Probabilistic Timing Analysis for Multi-path Programs
The rigorous application of static timing analysis requires a large and costly amount of detail knowledge on the hardware and software components of the system. Probabilistic Timing Analysis hasExpand
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A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation of a Space Case Study
Multicore Dual-Criticality systems comprise two types of applications, each with a different criticality level. In the space domain these types are referred as payload and control applications, whichExpand
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Hardware support for WCET analysis of hard real-time multicore systems
The increasing demand for new functionalities in current and future hard real-time embedded systems like automotive, avionics and space industries is driving an increase in the performance requiredExpand
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A cache design for probabilistically analysable real-time systems
Caches provide significant performance improvements, though their use in real-time industry is low because current WCET analysis tools require detailed knowledge of program's cache accesses toExpand
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PROARTIS: Probabilistically Analyzable Real-Time Systems
Static timing analysis is the state-of-the-art practice of ascertaining the timing behavior of current-generation real-time embedded systems. The adoption of more complex hardware to respond to theExpand
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Using Randomized Caches in Probabilistic Real-Time Systems
While hardware caches are generally effective at improving application performance, they greatly complicate performance prediction. Slight changes in memory layout or data access patterns can lead toExpand
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Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability
The Merasa project aims to achieve a breakthrough in hardware design, hard real-time support in system software, and worst-case execution time analysis tools for embedded multicore processors. TheExpand
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Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions
Multicore processors are an effective solution to cope with the performance requirements of real-time embedded systems due to their good performance-per-watt ratio and high performance capabilities.Expand
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