Clock signal

Known as: Central clock, Clock distribution network, Clock distribution netoworks 
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low… (More)
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Papers overview

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Review
2010
Review
2010
Most physiology and behavior of mammalian organisms follow daily oscillations. These rhythmic processes are governed by… (More)
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Highly Cited
2009
Highly Cited
2009
A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power… (More)
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Highly Cited
2003
Highly Cited
2003
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control… (More)
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Highly Cited
2002
Highly Cited
2002
A wireless interconnect system which transmits and receives RF signals across a chip using integrated antennas, receivers, and… (More)
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Highly Cited
2002
Highly Cited
2002
As clock frequency increases and feature size decreases, clock distribution and wire delays present a growing challenge to the… (More)
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Highly Cited
2001
Highly Cited
2001
In this paper, we investigate reducing the power consumption of a synchronous digital system by minimizing the total power… (More)
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Highly Cited
2000
Highly Cited
2000
  • VikasAgarwal M.S.Hrishikesh
  • 2000
Thedoublingof microprocessorperformanceeverythreeyearshasbeen theresultof two factors: more transistors per chip… (More)
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Highly Cited
1996
Highly Cited
1996
1A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI… (More)
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Highly Cited
1992
Highly Cited
1992
In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally… (More)
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Highly Cited
1987
Highly Cited
1987
We present a simple, efficient, and unified solution to the problems of synchronizing, initializing, and integrating clocks for… (More)
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