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Clock signal

Known as: Central clock, Clock distribution network, Clock distribution netoworks 
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low… 
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Related topics

Related topics

50 relations
Apollo Guidance ComputerArithmetic logic unitClock gatingClock rate

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2012
Highly Cited
2012
Environment-aware clock skew estimation and synchronization for wireless sensor networks
Clock synchronization is a fundamental requirement for network systems. It is particularly crucial and challenging in wireless… 
2009
2009
Cryptography Overhead Evaluation and Analysis for Wireless Sensor Networks
Security is a critical factor to deploy large scale wireless sensor networks. Limited resource constraints, such as computation… 
2007
2007
GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors
Due to the technological progress in the semiconductor industry, more and more components can be integrated on a single die… 
Highly Cited
2007
Highly Cited
2007
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs
Multimedia applications, and in particular the encoding and decoding of standard image and video formats, are usually a typical… 
2005
2005
A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC
We propose a hardware accelerator for context-based adaptive binary arithmetic decoding (CABAC) in H.264/AVC. We also propose an… 
2002
2002
Using rewriting rules and positive equality to formally verify wide-issue out-of-order microprocessors with a reorder buffer
  • M. Velev
  • Proceedings Design, Automation and Test in…
  • 2002
  • Corpus ID: 14933899
Rewriting rules and positive equality are combined in an automatic way in order to formally verify out-of-order processors that… 
1999
1999
A high resolution digital CMOS time-to-digital converter based on nested delay locked loops
This paper describes an integrated digital CMOS time-to-digital converter, TDC, with sub-gate-delay LSB width and 50 ps single… 
1998
1998
A 32×32-b adiabatic register file with supply clock generator
A 32/spl times/32-b adiabatic register file with one read port and one write port is designed. A four-phase clock generator is… 
Highly Cited
1989
Highly Cited
1989
Efficient one-dimensional systolic array realization of the discrete Fourier transform
A one-dimensional systolic array realizing the discrete Fourier transform (DFT) of nonstop input sequences is presented. Two… 
Highly Cited
1980
Highly Cited
1980
Practical implementation of a general computer aided design technique for switched capacitor circuits
A general and efficient CAD method for simulation of switched capacitor filters and A/D and D/A converters, is demonstrated. It…