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With the current trend in integration of more complex systems on chip there is a need for better communication infrastructure on chip that will increase the available band-width and simplify the interface verification. We have previously proposed a circuit switched two-dimensional mesh network known as SoCBUS that increases performance and lowers the cost(More)
—In this paper, hardware implementation aspects of the channel estimator in 3GPP LTE terminals are investigated. A channel estimation ASIC, which handles the real-time channel estimation, is presented. Compared to traditional correlator-based channel estimators, the channel estimator presented boosts the throughput at feasible silicon cost by adopting a(More)
— Complex matrix inversion is a very computationally demanding operation in advanced multi-antenna wireless communications. Traditionally, systolic array-based QR decomposition (QRD) is used to invert large matrices. However, the matrices involved in MIMO baseband processing in mobile handsets are generally small which means QRD is not necessarily(More)
This paper presents a case study of a single-chip 3G WCDMA/FDD basestation implementation based on a circuit-switched network on chip. As the amount of transistors on a chip continues to increase, so does the possibility to integrate more functionality onto every chip. By combining general-purpose and application-specific hardware , it is possible to(More)