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Clock gating

Known as: CG, Gating, Perfect clock gating 
Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating saves power by adding more… Expand
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Papers overview

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Highly Cited
2013
Highly Cited
2013
This paper presents an ultra-low power batteryless energy harvesting body sensor node (BSN) SoC fabricated in a commercial 130 nm… Expand
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Highly Cited
2011
Highly Cited
2011
amplitude of task-related power changes of EEG during motor imagery was recorded to assess the downstream modulation of primary… Expand
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Highly Cited
2009
Highly Cited
2009
A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power… Expand
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Highly Cited
2007
Highly Cited
2007
This paper analyzes the performance of concurrent (index) scan operations in both record (NSM/PAX) and column (DSM) disk storage… Expand
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Highly Cited
2006
Highly Cited
2006
In this paper, we describe a technique for delivering power to a digital integrated circuit at high voltages, reducing current… Expand
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Highly Cited
2003
Highly Cited
2003
The performance and power optimization of dynamic superscalar microprocessors requires striking a careful balance between… Expand
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Highly Cited
2002
Highly Cited
2002
Latent inhibition (LI) is a preconscious gating mechanism that allows animals with complex nervous systems to ignore stimuli… Expand
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Highly Cited
2001
Highly Cited
2001
The power dissipation of modern processors has been rapidly increasing along with increasing transistor count and clock… Expand
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Highly Cited
2001
Highly Cited
2001
Develops a methodology for selecting and optimizing flip-flops for low-energy systems with constant throughput. Characterization… Expand
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Highly Cited
2000
Highly Cited
2000
This paper models the clock behavior in a sequential circuit by a quaternary variable and uses this representation to propose and… Expand
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