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Clock gating
Known as:
CG
, Gating
, Perfect clock gating
Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating saves power by adding more…
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Related topics
Related topics
19 relations
AMD 10h
AMD Accelerated Processing Unit
Asynchronous circuit
CPU power dissipation
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Broader (1)
Electronic design automation
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
Analysis of Clock Gating and Power Gating Techniques on Sequential Circuits
Umpala
,
Rikanth
2015
Corpus ID: 35253498
In Integrated circuits a maximum portion of chip power is expended by clocking system which comprises of timing elements such as…
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2011
2011
Optimizing and Applying Graphene as a Saturable Absorber for Generating Ultrashort Pulses
J. Miller
2011
Corpus ID: 138565596
Graphene is a broadband, fast saturable absorber well suited for passive mode-locking of lasers. The broadband absorption, ultra…
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2009
2009
Clock gating effectiveness metrics: Applications to power optimization
Jithendra Srinivas
,
M. Rao
,
S. Jairam
,
H. Udayakumar
,
J. Rao
IEEE International Symposium on Quality…
2009
Corpus ID: 7575045
Effective implementation and efficient utilization of clock gating logic is a critical element for dynamic power optimization. In…
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2009
2009
Improve clock gating through power-optimal enable function selection
Juanjuan Chen
,
Xing Wei
,
Yunjian Jiang
,
Qiang Zhou
12th International Symposium on Design and…
2009
Corpus ID: 34640727
Clock gating technology can reduce the consumption of clock signals' switching power of flip-flops. The clock gate enable…
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2008
2008
Type-matching clock tree for zero skew clock gating
Chia-Ming Chang
,
Shih-Hsu Huang
,
Yuan-Kai Ho
,
Jia-Zong Lin
,
Hsin-Po Wang
,
Yu-Sheng Lu
45th ACM/IEEE Design Automation Conference
2008
Corpus ID: 1385207
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include…
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Review
2008
Review
2008
Clock gating for power optimization in ASIC design cycle theory & practice
S. Jairam
,
M. Rao
,
Jithendra Srinivas
,
Parimala Vishwanath
,
H. Udayakumar
,
J. Rao
International Symposium on Low Power Electronics…
2008
Corpus ID: 12027386
In this tutorial we present a comprehensive analysis of the available clock gate (CG) optimization approaches with re-cent…
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2007
2007
Low Power Circuit Architecture of AES Crypto Module for Wireless Sensor Network
Mooseop Kim
,
Ju-Han Kim
,
Yong-je Choi
2007
Corpus ID: 10910298
— Recently, much research has been conducted for security for wireless sensor networks and ubiquitous computing. Security issues…
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2002
2002
Efficient ASIC implementation of a WCDMA Rake Receiver
M. Nilsson
2002
Corpus ID: 16498990
This thesis is a study of a efficient ASIC implementation of a WCDMA Rake Receiver for the third generation mobile communication…
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2000
2000
Advanced Navigator Techniques
K. Nehrke
,
D. Manke
2000
Corpus ID: 18459874
The purpose of this study was to investigate and to optimize the performance of the real-time navigator technology on a clinical…
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Review
1998
Review
1998
A Comprehensive Framework for Model Based Diagnosis
P. Mosterman
,
G. Biswas
,
Manders E.-J.
1998
Corpus ID: 12881582
This paper reviews our work on monitoring, prediction, and fault isolation methods for complex dynamic systems affected by abrupt…
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