Clock gating

Known as: CG, Gating, Perfect clock gating 
Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating saves power by adding more… (More)
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2011
2011
A pulsed-latch is an ideal sequencing element for low-power ASIC designs due to its smaller capacitance and simple timing model… (More)
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2011
2011
Clock gating is one of the power-saving techniques used on the Pentium 4 processor and in next generation processors. To save… (More)
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Highly Cited
2009
Highly Cited
2009
A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power… (More)
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2009
2009
In this paper we consider the problem of exploiting infeasible clock gating functions. Analysis of industrial designs reveals a… (More)
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2008
2008
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include… (More)
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2007
2007
Clock gating is an effective technique for minimizing dynamic power in sequential circuits. Applying clock-gating at gate-level… (More)
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2006
2006
Clock-gating has been employed in low-power FPGA designs based on an emulated and compromised method. So far in literature the… (More)
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2004
2004
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major… (More)
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Highly Cited
2003
Highly Cited
2003
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control… (More)
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Highly Cited
2003
Highly Cited
2003
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major… (More)
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