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Clock gating
Known as:
CG
, Gating
, Perfect clock gating
Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating saves power by adding more…
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Related topics
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19 relations
AMD 10h
AMD Accelerated Processing Unit
Asynchronous circuit
CPU power dissipation
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Broader (1)
Electronic design automation
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
A high performance SEU-tolerant latch for nanoscale CMOS technology
Zhengfeng Huang
Design, Automation and Test in Europe
2014
Corpus ID: 2387268
This paper presents a high performance latch to tolerate radiation-induced single event upset in 45 nm CMOS technology. The latch…
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2010
2010
Area-Efficient Temporally Hardened by Design Flip-Flop Circuits
Bradley I Matush
,
T. Mozdzen
,
L. Clark
,
Jonathan E. Knudsen
IEEE Transactions on Nuclear Science
2010
Corpus ID: 30749056
Two temporally hardened master-slave flip-flops are presented. Both designs utilize master latches containing Muller C-elements…
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2008
2008
Single photon avalanche photodiodes for near-infrared photon counting
M. Itzler
,
Xudong Jiang
,
R. Ben-Michael
,
B. Nyman
,
K. Slomkowski
SPIE OPTO
2008
Corpus ID: 34377450
InP-based single photon avalanche diodes (SPADs) have proven to be the most practical solution currently available for many…
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2008
2008
Activity and register placement aware gated clock network design
Weixiang Shen
,
Yici Cai
,
Xianlong Hong
,
Jiang Hu
ACM International Symposium on Physical Design
2008
Corpus ID: 11469913
Clock gating is one of the most effective techniques to reduce clock network power dissipation. Although it has already been…
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2008
2008
Type-matching clock tree for zero skew clock gating
Chia-Ming Chang
,
Shih-Hsu Huang
,
Yuan-Kai Ho
,
Jia-Zong Lin
,
Hsin-Po Wang
,
Yu-Sheng Lu
45th ACM/IEEE Design Automation Conference
2008
Corpus ID: 1385207
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include…
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2005
2005
Teaching low-power electronic design in electrical and computer engineering
Jiann-Shiun Yuan
,
J. Di
IEEE Transactions on Education
2005
Corpus ID: 40634262
Because of the continuous scaling of feature size and the increasing demand of mobile communication devices, power dissipation…
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2004
2004
An electromigration and thermal model of power wires for a priori high-level reliability prediction
M. Casu
,
M. Graziano
,
G. Masera
,
G. Piccinini
,
M. Zamboni
IEEE Transactions on Very Large Scale Integration…
2004
Corpus ID: 17798974
In this paper, a simple power-distribution electrothermal model including the interconnect self-heating is used together with a…
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2003
2003
Comparing the Energy Efficiency of CMP and SMT Architectures for Multimedia Workloads
Ruchira Sasanka
,
S. Adve
,
Yen-kuang Chen
,
E. Debes
2003
Corpus ID: 18036141
Chip multiprocessing (CMP) and simultaneous multithreading (SMT) are two recently adopted techniques for improving the throughput…
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1999
1999
Numerical Simulation of Laser-Induced Fluorescence Imaging in Shock-Layer Flows
P. Danehy
,
P. Palma
,
R. Boyce
,
A. Houwing
1999
Corpus ID: 861044
Planar laser-induced fluorescence (PLIF) images of nitric oxide in hypersonic flow over a wedge and a hemisphere are compared…
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1975
1975
Testing the Linearity of Response of Gated Photomultipliers in Wide Dynamic Range Laser Radar Systems
W. Hunt
,
S. Poultney
IEEE Transactions on Nuclear Science
1975
Corpus ID: 9220899
Laser radar data acquisition systems have been utilized in conjunction with a light emitting diode to evaluate photomultipliers…
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