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Clock gating

Known as: CG, Gating, Perfect clock gating 
Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating saves power by adding more… 
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Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
This paper presents a high performance latch to tolerate radiation-induced single event upset in 45 nm CMOS technology. The latch… 
2010
2010
Two temporally hardened master-slave flip-flops are presented. Both designs utilize master latches containing Muller C-elements… 
2008
2008
InP-based single photon avalanche diodes (SPADs) have proven to be the most practical solution currently available for many… 
2008
2008
Clock gating is one of the most effective techniques to reduce clock network power dissipation. Although it has already been… 
2008
2008
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include… 
2005
2005
Because of the continuous scaling of feature size and the increasing demand of mobile communication devices, power dissipation… 
2004
2004
In this paper, a simple power-distribution electrothermal model including the interconnect self-heating is used together with a… 
2003
2003
Chip multiprocessing (CMP) and simultaneous multithreading (SMT) are two recently adopted techniques for improving the throughput… 
1999
1999
Planar laser-induced fluorescence (PLIF) images of nitric oxide in hypersonic flow over a wedge and a hemisphere are compared… 
1975
1975
Laser radar data acquisition systems have been utilized in conjunction with a light emitting diode to evaluate photomultipliers…