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AMD 10h
Known as:
AMD Barcelona
, Agena (processor)
, Barcelona processor
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The AMD Family 10h, or K10, is a microprocessor microarchitecture by AMD based on the K8 microarchitecture. Though there were once reports that the…
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AMD K8
Athlon
BIOS
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2012
2012
Inhibition of Advanced Glycation End Product Formation by Herbal Teas and Its Relation to Anti-Skin Aging
Mio Hori
,
M. Yagi
,
K. Nomoto
,
Akihiko Shimode
,
Mari Ogura
,
Y. Yonei
2012
Corpus ID: 16845199
Aims: Advanced glycation end product (AGE) accumulation in the body has been linked to the progression of aging and age-related…
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2011
2011
Evaluation and optimization of multicore performance bottlenecks in supercomputing applications
Jeff Diamond
,
Martin Burtscher
,
John D. McCalpin
,
Byoung-Do Kim
,
S. Keckler
,
J. Browne
(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON…
2011
Corpus ID: 14064554
The computation nodes of modern supercomputers commonly consist of multiple multicore processors. To maximize the performance of…
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Highly Cited
2010
Highly Cited
2010
An auto-tuning framework for parallel multicore stencil computations
S. Kamil
,
Cy P. Chan
,
L. Oliker
,
J. Shalf
,
Samuel Williams
IEEE International Symposium on Parallel…
2010
Corpus ID: 10088651
Although stencil auto-tuning has shown tremendous potential in effectively utilizing architectural resources, it has hitherto…
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2010
2010
Performance impact of resource contention in multicore systems
R. Hood
,
Haoqiang Jin
,
+6 authors
R. Biswas
IEEE International Symposium on Parallel…
2010
Corpus ID: 10676157
Resource sharing in commodity multicore processors can have a significant impact on the performance of production applications…
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2010
2010
NCID: a non-inclusive cache, inclusive directory architecture for flexible and efficient cache hierarchies
Li Zhao
,
R. Iyer
,
S. Makineni
,
D. Newell
,
Liqun Cheng
CF '10
2010
Corpus ID: 17402705
Chip-multiprocessor (CMP) architectures employ multi-level cache hierarchies with private L2 caches per core and a shared L3…
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Highly Cited
2009
Highly Cited
2009
Fine-grain Parallelism Using Multi-core, Cell/BE, and GPU Systems: Accelerating the Phylogenetic Likelihood Function
Frederico Pratas
,
Pedro Trancoso
,
A. Stamatakis
,
L. Sousa
International Conference on Parallel Processing
2009
Corpus ID: 6187772
We are currently faced with the situation where applications have increasing computational demands and there is a wide selection…
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Highly Cited
2009
Highly Cited
2009
Auto-tuning stencil codes for cache-based multicore platforms
K. Yelick
,
K. Datta
2009
Corpus ID: 30935145
As clock frequencies have tapered off and the number of cores on a chip has taken off, the challenge of effectively utilizing…
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2009
2009
Computing discrete transforms on the Cell Broadband Engine
David A. Bader
,
Virat Agarwal
,
Seunghwa Kang
Parallel Comput.
2009
Corpus ID: 46678
2008
2008
pOSKI : An Extensible Autotuning Framework to Perform Optimized SpMVs on Multicore Architectures
Ankit Jain
2008
Corpus ID: 1089421
We have developed pOSKI: the Parallel Optimized Sparse Kernel Interface – an autotuning framework to optimize Sparse Matrix…
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Highly Cited
2005
Highly Cited
2005
GRB 050509B: Constraints on Short Gamma-Ray Burst Models
J. Hjorth
,
J. Sollerman
,
+19 authors
R. Wijers
2005
Corpus ID: 17532533
We have obtained deep optical images with the Very Large Telescope at ESO of the first well-localized short-duration gamma-ray…
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