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Clock skew
Known as:
Clock shear
, Skew
, Timing skew
The operation of most digital circuit systems, such as computer systems, is synchronized by a periodic signal known as a "clock" that dictates the…
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Related topics
Related topics
24 relations
Clock drift
Clock signal
Combinational logic
Computer
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2012
Highly Cited
2012
Environment-aware clock skew estimation and synchronization for wireless sensor networks
Zhe Yang
,
Lin X. Cai
,
Yu Liu
,
Jianping Pan
Proceedings IEEE INFOCOM
2012
Corpus ID: 17507069
Clock synchronization is a fundamental requirement for network systems. It is particularly crucial and challenging in wireless…
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Review
2012
Review
2012
Design methods and considerations of supply modulated switched RF power amplifiers
S. Hietakangas
2012
Corpus ID: 61798005
This thesis studies the design methods and properties of supply-modulated switch-mode radio frequency power amplifiers. Besides…
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2012
2012
IMPLEMENTATION OF SYNCHRONOUS UP COUNTER BY USING SELF RESETTING LOGIC
V. Bhaskar
,
S. Suparshya Babu
,
Susrutha Babu Sukhavasi
,
G. Vemana
2012
Corpus ID: 18328022
Self-resetting logic is a commonly used piece of circuitry that can be found in use with memory arrays as word line drivers. Self…
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2012
2012
An Extensible and Secure Framework for Distributed Applications
Aneesh Sharma
,
Shilpi Gupta
2012
Corpus ID: 2863972
Availability, Scalability, Reliability, Security and resource sharing are the key issues for success of any application, that are…
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2009
2009
Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies
J. Semião
,
J. Freijedo
,
+4 authors
João Paulo Teixeira
15th IEEE International On-Line Testing Symposium
2009
Corpus ID: 9058951
In nanometer technologies, as variability is becoming one of the leading causes for chip failures, signal integrity is a key…
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2008
2008
Type-matching clock tree for zero skew clock gating
Chia-Ming Chang
,
Shih-Hsu Huang
,
Yuan-Kai Ho
,
Jia-Zong Lin
,
Hsin-Po Wang
,
Yu-Sheng Lu
45th ACM/IEEE Design Automation Conference
2008
Corpus ID: 1385207
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include…
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2006
2006
Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding
M. Badaroglu
,
K. Tiri
,
+5 authors
H. Man
IEEE Transactions on Computer-Aided Design of…
2006
Corpus ID: 1279809
In a synchronous clock distribution network with negligible skews, digital circuits switch simultaneously on the clock edge…
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2005
2005
Fast interval-valued statistical interconnect modeling and reduction
James D. Z. Ma
,
Rob A. Rutenbar
ACM International Symposium on Physical Design
2005
Corpus ID: 18902968
Correlated interval representations of range uncertainty offer an attractive solution for approximating computations on…
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2000
2000
Multiclock Esterel: a reactive framework for asynchronous design
Basant Rajan
,
R. Shyamasundar
Proceedings, International Parallel and…
2000
Corpus ID: 896756
In this paper, we discuss a new paradigm called Multiclock Esterel, based on the paradigm of the synchronous reactive language…
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1999
1999
The D30V/MPEG multimedia processor
H. Takata
,
T. Watanabe
,
+8 authors
Y. Horiba
IEEE Micro
1999
Corpus ID: 206433538
MPEG-2 decoding and encoding are important applications for multimedia systems. Real-time capability and low-cost implementation…
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