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Clock skew

Known as: Clock shear, Skew, Timing skew 
The operation of most digital circuit systems, such as computer systems, is synchronized by a periodic signal known as a "clock" that dictates the… 
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Related topics

Related topics

24 relations
Clock driftClock signalCombinational logicComputer

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2008
2008
Type-matching clock tree for zero skew clock gating
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include… 
2005
2005
Time-delay optimization of RSFQ cells
This paper presents timing models for RSFQ cells, based on conventional finite-state machines description. Models have been… 
2004
2004
Fast feedthrough logic: a high performance logic family for GaAs
A GaAs dynamic logic family using the feedthrough evaluation concept is presented in this paper. Feedthrough logic (FTL) allows… 
Highly Cited
2002
Highly Cited
2002
Diagnosis of sequence-dependent chips
  • C. LiE. McCluskey
  • Proceedings 20th IEEE VLSI Test Symposium (VTS )
  • 2002
  • Corpus ID: 31910146
A technique capable of diagnosing single and multiple stuck-open and stuck-at faults is presented. Eleven sequence-dependent… 
Review
2002
Review
2002
On-chip inductance cons and pros
  • Y. Ismail
  • IEEE Transactions on Very Large Scale Integration…
  • 2002
  • Corpus ID: 6560683
Provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and… 
Highly Cited
2002
Highly Cited
2002
Power supply noise suppression via clock skew scheduling
Simultaneous switching events in the clock lines and the signals passing through sequential and combinational logic elements… 
Highly Cited
2001
Highly Cited
2001
Statistical clock skew modeling with data delay variations
Accurate clock skew budgets are important for microprocessor designers to avoid hold-time failures and to properly allocate… 
1999
1999
Timing analysis including clock skew
Clock skew is an increasing concern for high-speed circuit designers. Circuit designers use transparent latches and skew-tolerant… 
1993
1993
Topological design of clock distribution networks based on non-zero clock skew specifications
  • J. NevesE. Friedman
  • Proceedings of 36th Midwest Symposium on Circuits…
  • 1993
  • Corpus ID: 61041434
A methodology is presented in this paper for designing clock distribution networks based on application dependent clock skew… 
Highly Cited
1986
Highly Cited
1986
Elimination of process-dependent clock skew in CMOS VLSI
Delays of two clock signals propagating along their respective CMOS logic circuit paths can be matched against all processing… 
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