• Publications
  • Influence
Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies
The IMPLY logic gate, a memristor-based logic circuit, is described and a methodology for designing this logic family is proposed, based on a general design flow suitable for all deterministic memristive logic families.
MAGIC—Memristor-Aided Logic
In this brief, a memristor-only logic family, i.e., memristar-aided logic (MAGIC), is presented, and in each MAGIC logic gate, memristors serve as an input with previously stored data, and an additional Memristor serves as an output.
TEAM: ThrEshold Adaptive Memristor Model
It is shown that the proposed TEAM, ThrEshold Adaptive Memristor model is reasonably accurate and computationally efficient, and is more appropriate for circuit simulation than previously published models.
VTEAM: A General Model for Voltage-Controlled Memristors
The VTEAM model extends the previously proposed ThrEshold Adaptive Memristor (TEAM) model, which describes current-controlled memristors and has similar advantages as the TEAM model, i.e., it is simple, general, and flexible, and can characterize different voltage-controlled Memristors.
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
  • Y. Ismail, E. Friedman
  • Engineering, Computer Science
    IEEE Trans. Very Large Scale Integr. Syst.
  • 1 April 2000
The importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale, as the error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling.
System Timing
3-D Topologies for Networks-on-Chip
An analytic model for the zero-load latency of each network that considers the effects of the topology on the performance of a 3D NoC is developed and the number of physical planes used to integrate the functional blocks of the network is evaluated for both the latency and power consumption of a network.
Three-dimensional Integrated Circuit Design
With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a
MRL — Memristor Ratioed Logic
This paper describes MRL (Memristor Ratioed Logic) - a hybrid CMOS-memristive logic family, in which OR and AND logic gates are based on memristive devices, and CMOS inverters are added to provide a complete logic structure and signal restoration.
Clock distribution networks in synchronous digital integrated circuits
A theoretical background of clock skew is provided and minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths.