Skip to search formSkip to main contentSkip to account menu

Combinational logic

Known as: Combinatorial circuit, Combinational, Combinatorial logic (electronics) 
In digital circuit theory, combinational logic (sometimes also referred to as time-independent logic) is a type of digital logic which is implemented… 
Wikipedia (opens in a new tab)

Related topics

Related topics

47 relations
Arithmetic logic unitAsynchronous circuitBinary decoderBoolean algebra

Broader (2)

Digital electronicsLogic in computer science

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2008
2008
HYPERSPECTRAL IMAGES FOR UNCERTAINTY INFORMATION INTERPRETATION BASED ON FUZZY CLUSTERING AND NEURAL NETWORK
Effective and understanding exploration of hyperspectral remote sensing data necessitates the development of sophisticated… 
2003
2003
Analysis and design of optimal combinational compactors [logic test]
Scan and logic built-in self-test (BIST) are increasingly used to reduce test cost. In these test architectures, many internal… 
Highly Cited
2000
Highly Cited
2000
Testing, verification, and diagnosis in the presence of unknowns
Improvement of the accuracy of error and fault diagnosis as well as ATPG for IP-based designs are important problems in industry… 
2000
2000
Simultaneous gate sizing and placement
This paper presents an iterative optimization technique for improving delay in integrated circuits. The basic idea is to perform… 
Highly Cited
1999
Highly Cited
1999
A test vector ordering technique for switching activity reduction during test operation
This paper considers the problem of testing VLSI integrated circuits without exceeding their power ratings during test. The… 
Highly Cited
1999
Highly Cited
1999
On calculating efficient LFSR seeds for built-in self test
Linear Feedback Shift Registers (LFSRs) are commonly used as pseudo-random test pattern generators (TPGs) in BIST schemes. This… 
Highly Cited
1991
Highly Cited
1991
Performance trade-offs in a parallel test generation/fault simulation environment
Heuristics are proposed to partition faults for parallel test generation with minimization of both the overall run time and test… 
1991
1991
A test-pattern-generation algorithm for sequential circuits
A deterministic test-pattern-generation algorithm for synchronous sequential circuits is presented. The algorithm, called… 
Highly Cited
1988
Highly Cited
1988
CONTEST: a concurrent test generator for sequential circuits
The application of a concurrent fault simulator to automatic test vector generation is described. As faults are simulated in the… 
1985
1985
The Error Latency of Delay Faults in Combinational and Sequential Circuits