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Combinational logic
Known as:
Combinatorial circuit
, Combinational
, Combinatorial logic (electronics)
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In digital circuit theory, combinational logic (sometimes also referred to as time-independent logic) is a type of digital logic which is implemented…
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Related topics
Related topics
47 relations
Arithmetic logic unit
Asynchronous circuit
Binary decoder
Boolean algebra
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Broader (2)
Digital electronics
Logic in computer science
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2002
Highly Cited
2002
An efficient test relaxation technique for combinational & full-scan sequential circuits
A. El-Maleh
,
Ali Al-Suwaiyan
Proceedings 20th IEEE VLSI Test Symposium (VTS )
2002
Corpus ID: 18691174
Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test…
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2000
2000
Ant Colony System for the Design of Combinational Logic Circuits
C. C. Coello
,
R. Gutierrez
,
B. M. García
,
A. H. Aguirre
International Conference on Evolvable Systems
2000
Corpus ID: 30291985
In this paper we propose an application of the Ant System (AS) to optimize combinational logic circuits at the gate level. We…
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Highly Cited
1999
Highly Cited
1999
A test vector ordering technique for switching activity reduction during test operation
P. Girard
,
L. Guiller
,
C. Landrault
,
S. Pravossoudovitch
Proceedings Ninth Great Lakes Symposium on VLSI
1999
Corpus ID: 31534073
This paper considers the problem of testing VLSI integrated circuits without exceeding their power ratings during test. The…
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Highly Cited
1999
Highly Cited
1999
Low Power BIST by Filtering Non-Detecting Vectors
S. Manich
,
A. Gabarró
,
+7 authors
Marcelino B. Santos
European Test Workshop (Cat. No.PR00390)
1999
Corpus ID: 17848007
In this paper, two techniques to reduce the energy and the average power consumption of the system are proposed. They are based…
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Highly Cited
1998
Highly Cited
1998
Using a single input to support multiple scan chains
Kuen-Jong Lee
,
Jih-Jeen Chen
,
Cheng-Hua Huang
International Conference on Computer Aided Design
1998
Corpus ID: 10563352
Single scan chain architectures suffer from long test application time, while multiple scan chain architectures require large pin…
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Highly Cited
1994
Highly Cited
1994
Application of simple genetic algorithms to sequential circuit test generation
E. Rudnick
,
J. Holm
,
D. Saab
,
J. Patel
Proceedings of European Design and Test…
1994
Corpus ID: 13140902
In this work we investigate the effectiveness of genetic algorithms (GAs) in the test generation process. We use simple GAs to…
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Highly Cited
1992
Highly Cited
1992
E-PROOFS: A CMOS bridging fault simulator
G. S. Greenstein
,
J. Patel
IEEE/ACM International Conference on Computer…
1992
Corpus ID: 16461891
The problem of bridging fault simulation under the conventional voltage testing environment is considered. A method to provide…
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Highly Cited
1991
Highly Cited
1991
CAREL: Computer Aided Reliability Evaluator for Distributed Computing Networks
S. Soh
,
S. Rai
IEEE Trans. Parallel Distributed Syst.
1991
Corpus ID: 1132635
An efficient method to compute the terminal reliability (the probability of communication between a pair of nodes) of a…
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Highly Cited
1976
Highly Cited
1976
Transition Count Testing of Combinational Logic Circuits
J. Hayes
IEEE transactions on computers
1976
Corpus ID: 206621034
Logic circuits are usually tested by applying a sequence of input patterns S to the circuit under test and comparing the observed…
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Review
1968
Review
1968
Fault Testing and Diagnosis in Combinational Digital Circuits
W. Kautz
IEEE transactions on computers
1968
Corpus ID: 52800401
Abstract—he problem of designing test schedules for the testing or diagnosis of a small number of nontransient faults in…
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