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Combinational logic
Known as:
Combinatorial circuit
, Combinational
, Combinatorial logic (electronics)
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In digital circuit theory, combinational logic (sometimes also referred to as time-independent logic) is a type of digital logic which is implemented…
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Related topics
Related topics
47 relations
Arithmetic logic unit
Asynchronous circuit
Binary decoder
Boolean algebra
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Broader (2)
Digital electronics
Logic in computer science
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2000
2000
Simultaneous gate sizing and placement
Wei Chen
,
Cheng-Ta Hsieh
,
Massoud Pedram
IEEE Trans. Comput. Aided Des. Integr. Circuits…
2000
Corpus ID: 2753220
This paper presents an iterative optimization technique for improving delay in integrated circuits. The basic idea is to perform…
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Highly Cited
1999
Highly Cited
1999
A test vector ordering technique for switching activity reduction during test operation
P. Girard
,
L. Guiller
,
C. Landrault
,
S. Pravossoudovitch
Proceedings Ninth Great Lakes Symposium on VLSI
1999
Corpus ID: 31534073
This paper considers the problem of testing VLSI integrated circuits without exceeding their power ratings during test. The…
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Highly Cited
1999
Highly Cited
1999
Low Power BIST by Filtering Non-Detecting Vectors
S. Manich
,
A. Gabarró
,
+7 authors
Marcelino B. Santos
European Test Workshop (Cat. No.PR00390)
1999
Corpus ID: 17848007
In this paper, two techniques to reduce the energy and the average power consumption of the system are proposed. They are based…
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Highly Cited
1999
Highly Cited
1999
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity
P. Girard
,
L. Guiller
,
+5 authors
Marcelino B. Santos
ISCAS'99. Proceedings of the IEEE International…
1999
Corpus ID: 43351090
Low-power design looks for low-energy BIST. This paper considers the problem of minimizing the energy required to test a BISTed…
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Highly Cited
1999
Highly Cited
1999
On calculating efficient LFSR seeds for built-in self test
C. Fagot
,
O. Gascuel
,
P. Girard
,
C. Landrault
European Test Workshop (Cat. No.PR00390)
1999
Corpus ID: 15409833
Linear Feedback Shift Registers (LFSRs) are commonly used as pseudo-random test pattern generators (TPGs) in BIST schemes. This…
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1991
1991
A test-pattern-generation algorithm for sequential circuits
E. Auth
,
M. Schulz
IEEE Design & Test of Computers
1991
Corpus ID: 35799899
A deterministic test-pattern-generation algorithm for synchronous sequential circuits is presented. The algorithm, called…
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Highly Cited
1991
Highly Cited
1991
Performance trade-offs in a parallel test generation/fault simulation environment
S. Patil
,
P. Banerjee
IEEE Trans. Comput. Aided Des. Integr. Circuits…
1991
Corpus ID: 22299239
Heuristics are proposed to partition faults for parallel test generation with minimization of both the overall run time and test…
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Highly Cited
1988
Highly Cited
1988
CONTEST: a concurrent test generator for sequential circuits
V. Agrawal
,
K. Cheng
,
P. Agrawal
25th ACM/IEEE, Design Automation Conference…
1988
Corpus ID: 6645024
The application of a concurrent fault simulator to automatic test vector generation is described. As faults are simulated in the…
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Highly Cited
1981
Highly Cited
1981
Multiple Fault Testing of Large Circuits by Single Fault Test Sets
V. Agarwal
,
A. Fung
IEEE transactions on computers
1981
Corpus ID: 34284123
A general theory is presented in this paper to quantitatively predict the multiple fault coverage capability of single fault…
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1974
1974
Diagnosis of Short-Circuit Faults in Combinational Circuits
A. D. Friedman
IEEE transactions on computers
1974
Corpus ID: 35719403
Most work on diagnosis of digital circuits has concentrated on the model of stuck-type faults. Although these faults are probably…
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