Skip to search form
Skip to main content
Skip to account menu
Semantic Scholar
Semantic Scholar's Logo
Search 238,733,652 papers from all fields of science
Search
Sign In
Create Free Account
Combinational logic
Known as:
Combinatorial circuit
, Combinational
, Combinatorial logic (electronics)
Expand
In digital circuit theory, combinational logic (sometimes also referred to as time-independent logic) is a type of digital logic which is implemented…
Expand
Wikipedia
(opens in a new tab)
Create Alert
Alert
Related topics
Related topics
47 relations
Arithmetic logic unit
Asynchronous circuit
Binary decoder
Boolean algebra
Expand
Broader (2)
Digital electronics
Logic in computer science
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2010
2010
Creativity and Art: Three Roads to Surprise
M. Boden
2010
Corpus ID: 193880243
Margaret Boden presents a series of essays in which she explores the nature of creativity in a wide range of art forms…
Expand
2008
2008
HYPERSPECTRAL IMAGES FOR UNCERTAINTY INFORMATION INTERPRETATION BASED ON FUZZY CLUSTERING AND NEURAL NETWORK
Liao-Yuan Huan
,
Hongxia Luoa
,
Ziyi Zhub
,
Guangpeng Liua
2008
Corpus ID: 9394368
Effective and understanding exploration of hyperspectral remote sensing data necessitates the development of sophisticated…
Expand
2000
2000
Simultaneous gate sizing and placement
Wei Chen
,
Cheng-Ta Hsieh
,
Massoud Pedram
IEEE Trans. Comput. Aided Des. Integr. Circuits…
2000
Corpus ID: 2753220
This paper presents an iterative optimization technique for improving delay in integrated circuits. The basic idea is to perform…
Expand
Highly Cited
1999
Highly Cited
1999
On calculating efficient LFSR seeds for built-in self test
C. Fagot
,
O. Gascuel
,
P. Girard
,
C. Landrault
European Test Workshop (Cat. No.PR00390)
1999
Corpus ID: 15409833
Linear Feedback Shift Registers (LFSRs) are commonly used as pseudo-random test pattern generators (TPGs) in BIST schemes. This…
Expand
1999
1999
Primitive delay faults: identification, testing, and design for testability
Angela Krstic
,
K. Cheng
,
Srimat T. Chakradhar
IEEE Trans. Comput. Aided Des. Integr. Circuits…
1999
Corpus ID: 15296665
We investigate two strategies to guarantee temporal correctness of a combinational circuit. We first propose a new technique to…
Expand
1995
1995
Low-Power Array Multipliers with Transition-Retaining Barriers
E. Musoll
,
J. Cortadella
1995
Corpus ID: 18198831
This paper presents a method for reducing the power dissipa-tion of array multipliers. It is based on the insertion of transition…
Expand
1991
1991
A test-pattern-generation algorithm for sequential circuits
E. Auth
,
M. Schulz
IEEE Design & Test of Computers
1991
Corpus ID: 35799899
A deterministic test-pattern-generation algorithm for synchronous sequential circuits is presented. The algorithm, called…
Expand
1991
1991
Fast functional evaluation of candidate OBDD variable orderings
D. Ross
,
K. Butler
,
R. Kapur
,
M. R. Mercer
Proceedings of the European Conference on Design…
1991
Corpus ID: 7160504
Symbolic simulation via ordered binary decision diagrams (OBDDs) is becoming more feasible each year. These representations are…
Expand
1989
1989
The parallel-test-detect fault simulation algorithm
Bill Underwood
,
Jack Ferguson
Proceedings. 'Meeting the Tests of Time…
1989
Corpus ID: 11526568
It is shown how the test-detect principle can be adapted to the parallel-patterns technique for combinational fault simulation…
Expand
1985
1985
The Error Latency of Delay Faults in Combinational and Sequential Circuits
K. Wagner
International Test Conference
1985
Corpus ID: 46382938