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Combinational logic

Known as: Combinatorial circuit, Combinational, Combinatorial logic (electronics) 
In digital circuit theory, combinational logic (sometimes also referred to as time-independent logic) is a type of digital logic which is implemented… 
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Related topics

Related topics

47 relations
Arithmetic logic unitAsynchronous circuitBinary decoderBoolean algebra

Broader (2)

Digital electronicsLogic in computer science

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2010
Highly Cited
2010
Design of AES S-box using combinational logic optimization
Advanced Encryption Standard (AES) is one of the most common symmetric encryption algorithms. The hardware complexity in AES is… 
Highly Cited
2002
Highly Cited
2002
An efficient test relaxation technique for combinational & full-scan sequential circuits
Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test… 
2000
2000
Ant Colony System for the Design of Combinational Logic Circuits
In this paper we propose an application of the Ant System (AS) to optimize combinational logic circuits at the gate level. We… 
Highly Cited
1999
Highly Cited
1999
A test vector ordering technique for switching activity reduction during test operation
This paper considers the problem of testing VLSI integrated circuits without exceeding their power ratings during test. The… 
Highly Cited
1999
Highly Cited
1999
Low Power BIST by Filtering Non-Detecting Vectors
In this paper, two techniques to reduce the energy and the average power consumption of the system are proposed. They are based… 
Highly Cited
1998
Highly Cited
1998
Using a single input to support multiple scan chains
Single scan chain architectures suffer from long test application time, while multiple scan chain architectures require large pin… 
Highly Cited
1992
Highly Cited
1992
CRIS: A test cultivation program for sequential VLSI circuits
An approach to cultivating a test for combinational and sequential VLSI circuits described hierarchically at the transistor, gate… 
Highly Cited
1992
Highly Cited
1992
E-PROOFS: A CMOS bridging fault simulator
The problem of bridging fault simulation under the conventional voltage testing environment is considered. A method to provide… 
Highly Cited
1991
Highly Cited
1991
CAREL: Computer Aided Reliability Evaluator for Distributed Computing Networks
  • S. SohS. Rai
  • IEEE Trans. Parallel Distributed Syst.
  • 1991
  • Corpus ID: 1132635
An efficient method to compute the terminal reliability (the probability of communication between a pair of nodes) of a… 
Highly Cited
1988
Highly Cited
1988
On the design of robust testable CMOS combinational logic circuits
  • S. KunduS. Reddy
  • [] The Eighteenth International Symposium on…
  • 1988
  • Corpus ID: 29763411
The authors propose an integrated approach to the design of combinational logic circuits in which stuck-open faults and path… 
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