• Publications
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Sequential circuit design using synthesis and optimization
A description is given of SIS, an interactive tool for synthesis and optimization of sequential circuits. Expand
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VIS: A System for Verification and Synthesis
We have described the verification and synthesis tool VIS, which offers a better programming environment, new capabilities, and improved performance over existing verification tools. Expand
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Combinational test generation using satisfiability
We present a robust, efficient algorithm for combinational test generation using a reduction to satisfiability (SAT). Expand
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MIS: A Multiple-Level Logic Optimization System
MIS is both an interactive and a batch-oriented multilevel logic synthesis and minimization system. Expand
  • 1,151
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Metropolis: An Integrated Electronic System Design Environment
Metropolis provides an environment for complex electronic-system design that supports simulation, formal analysis, and synthesis with formal semantics that developers can use to capture designs. Expand
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A framework for comparing models of computation
We give a denotational framework (a "meta model") within which certain properties of models of computation can be compared. Expand
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Hardware-software co-design of embedded systems: the POLIS approach
Embedded systems are informally defined as a collection of programmable parts surrounded by ASICs and other standard components, that interact continuously with an environment through sensors andExpand
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Steady-state methods for simulating analog and microwave circuits
We present the APFT Time-Point Selection Algorithm for Transform Matrix. Expand
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Multiple-Valued Minimization for PLA Optimization
This paper describes both a heuristic algorithm, Espresso-MV, and an exact algorithm for minimization of multiple-valued input, binary-valued output logic functions. Expand
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Theory of latency-insensitive design
The theory of latency-insensitive design is presented as the foundation of a new correct-by-construction methodology to design complex systems by assembling intellectual property components. Expand
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