• Publications
  • Influence
ABC: An Academic Industrial-Strength Verification Tool
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs ABC combines scalable logic transformations based on And-Inverter Graphs with a variety of innovative algorithms. Expand
  • 517
  • 97
  • PDF
Model-checking continuous-time Markov chains
We present a logical formalism for expressing properties of continuous-time Markov chains. Expand
  • 434
  • 88
  • PDF
Verifying Continuous Time Markov Chains
We present a logical formalism for expressing properties of continuous time Markov chains. Expand
  • 370
  • 61
Efficient implementation of property directed reachability
We present the first truly new bit-level symbolic model checking algorithm since Ken McMillan's interpolation based model checking procedure introduced in 2003. Expand
  • 272
  • 56
  • PDF
Sequential circuit design using synthesis and optimization
A description is given of SIS, an interactive tool for synthesis and optimization of sequential circuits. Expand
  • 597
  • 50
VIS: A System for Verification and Synthesis
We have described the verification and synthesis tool VIS, which offers a better programming environment, new capabilities, and improved performance over existing verification tools. Expand
  • 708
  • 48
  • PDF
A theory of nonlinear networks. I
This report describes a new approach to nonlinear RLC-networks which is based on the fact that the system of differential equations for such networks has the special form T/-x di dP(i, v) which has its ultimate basis in the conservation laws of Kirchhoff. Expand
  • 382
  • 46
  • PDF
Combinational test generation using satisfiability
We present a robust, efficient algorithm for combinational test generation using a reduction to satisfiability (SAT). Expand
  • 355
  • 43
  • PDF
MIS: A Multiple-Level Logic Optimization System
MIS is both an interactive and a batch-oriented multilevel logic synthesis and minimization system. Expand
  • 1,151
  • 42
DAG-aware AIG rewriting: a fresh look at combinational logic synthesis
This paper presents a technique for preprocessing combinational logic before technology mapping that scales to very large designs and is several orders of magnitude faster than SIS and MVSIS while offering comparable quality when measured by the quality of the network after mapping. Expand
  • 394
  • 36
  • PDF