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Binary decoder
Known as:
Line decoder
, Digital decoder
, Priority decoder
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In digital electronics, a binary decoder is a combinational logic circuit that converts a binary integer value to an associated pattern of output…
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Related topics
Related topics
19 relations
Address decoder
Artificial neural network
Binary-coded decimal
Combinational logic
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
Techniques for Turbo Decoding Using Parallel Processing, Comparative Analysis
R. Paper
,
Rupinder Kaur
,
Sarpreet Singh
2013
Corpus ID: 212542654
-Parallel turbo decoding is becoming mandatory in order to achieve high throughput and to reduce latency, both crucial in…
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2007
2007
A Bayesian Framework for Iterative Channel Estimation and Multiuser Decoding in Coded DS-CDMA
B. Hu
,
Ingmar Land
,
R. Piton
,
B. Fleury
IEEE GLOBECOM - IEEE Global Telecommunications…
2007
Corpus ID: 5924266
This paper deals with a novel design approach for a converging iterative receiver for coded CDMA that estimates both the channel…
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2005
2005
Decentralized Stabilization of Linear Systems via Limited Capacity Communication Networks
A. Matveev
,
A. Savkin
Proceedings of the 44th IEEE Conference on…
2005
Corpus ID: 16710292
The paper addresses feedback stabilization of discrete-time linear systems with multiple sensors, controllers, and actuators. The…
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2004
2004
Analog Sliding Window Decoder Core for Mixed Signal Turbo Decoder
M. Mörz
2004
Corpus ID: 16086090
The application of turbo codes in modern communication systems makes decoding a time and power consuming task. It is known that…
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1999
1999
Grouped-moduli residue number systems for fast signal processing
A. Skavantzos
,
T. Stouraitis
ISCAS'99. Proceedings of the IEEE International…
1999
Corpus ID: 36403448
In this paper a new class of multi-moduli residue number systems (RNS) and their efficient RNS-to-weighted converters are…
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1998
1998
Eecient Realizations of Encoders and Decoders Based on the 2-d Discrete Wavelet Transform
Clint MumfordAbstract
1998
Corpus ID: 6890681
| In this paper we present architectures and scheduling algorithms for encoders and decoders that are based on the 2-D Discrete…
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1997
1997
A high-speed asynchronous decompression circuit for embedded processors
Martin Benes
,
A. Wolfe
,
S. Nowick
Proceedings Seventeenth Conference on Advanced…
1997
Corpus ID: 15244508
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine…
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1991
1991
New VLSI architectures for fast soft-decision threshold decoders
P. Lavoie
,
D. Haccoun
,
Y. Savaria
IEEE Transactions on Communications
1991
Corpus ID: 7269220
New VLSI architectures for fast convolutional threshold decoders that process soft-quantized channel symbols are presented. The…
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1985
1985
Low Complexity Carrier Phase Tracking Decoders for Continuous Phase Modulations
S. Simmons
,
P. McLane
IEEE Transactions on Communications
1985
Corpus ID: 206637189
Phase tracking capability is incorporated into two sequence estimation decoders for continuous phase modulations. One decoder…
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1973
1973
Integrated techniques for functional and gate-level digital logic simulation
S. Szygenda
,
A. Lekkos
Design Automation Conference
1973
Corpus ID: 14492466
Digital simulation is defined as the process of exercising a realistic software model of a digital system, with sets of input…
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