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Address decoder

In digital electronics, an address decoder is a binary decoder that has two or more inputs for address bits and one or more outputs for device… 
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Related topics

18 relations
Address busApplication-specific integrated circuitBinary decoderBus (computing)

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
Leakage Power Estimation & Minimization In a 6T SRAM Cell Using Dual Vth, Dual Tox, & Stacking Techniques
Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep… 
2013
2013
Design Techniques and Tradeoffs of FinFET SRAM Memories
........................................................................................................................................ iv List of Tables ............................................................................................................................... xii List of Figures ............................................................................................................................. xvi Chapter 
2009
2009
Long-run Uncertainty and Value
2008
2008
Detection of address decoder faults
The invention relates to detection of failure of an address decoder. A memory 2 is formed having an array of memory cells 4… 
2006
2006
Low-leakage SRAM design with dual V/sub t/ transistors
This paper presents a method based on dual threshold voltage assignment to reduce the leakage power dissipation of SRAMs while… 
2004
2004
Built-In Self-Test Configurations for Atmel FPGAs Using Macro Generation Language
The development and automatic generation of Built-In Self-Test (BIST) configurations for Atmel AT40K series Field Programmable… 
2000
2000
Detection of Delay Faults in Memory Address Decoders
In this paper we present an efficient test concept for detection of delay faults in memory address decoders based on the march… 
1994
1994
Two-phase logic design by hardware flowcharts
Two-phase logic design is a technique that has long been used in the IC industry to increase data throughput and improve silicon… 
1994
1994
Fault models and tests for Ring Address Type FIFOs
First-in First-Out memories are becoming increasingly popular as buffer storage between subsystems operating at different data… 
1992
1992
An Architecture To Test Random Access Memories
  • R. Rajsuman
  • The Fifth International Conference on VLSI Design
  • 1992
  • Corpus ID: 33658623