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Address decoder

In digital electronics, an address decoder is a binary decoder that has two or more inputs for address bits and one or more outputs for device… 
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Related topics

Related topics

18 relations
Address busApplication-specific integrated circuitBinary decoderBus (computing)

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
Analog Digital Belief Propagation and its application to multi stage decoding systems
Next generation wireless systems will need to have higher spectral efficiency as the expected traffic volumes per unit bandwidth… 
2013
2013
A New March Test for Process-Variation Induced Delay Faults in SRAMs
Process variations are growing with technology scaling towards nano-scale. This brings new challenges to the design of memory… 
2011
2011
An Effective Test Algorithm and Diagnostic Implementation for Embedded Static Random Access Memories
An effective test algorithm and built-in self-test (BIST) with diagnostic support for embedded static random access memories… 
Highly Cited
2006
Highly Cited
2006
Reducing the Sub-threshold and Gate-tunneling Leakage of SRAM Cells using Dual-Vt and Dual-Tox Assignment
Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in very deep… 
2006
2006
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions
This paper presents a comparative analysis of ADOFs (Address Decoder Open Faults) and resistive-ADOFs in embedded-SRAMs. Such… 
2005
2005
Impact of stresses on the fault coverage of memory tests
Memory tests are applied in the industry using different algorithmic stresses (e.g., data-backgrounds) and non-algorithmic… 
2004
2004
Built-In Self-Test Configurations for Atmel FPGAs Using Macro Generation Language
The development and automatic generation of Built-In Self-Test (BIST) configurations for Atmel AT40K series Field Programmable… 
1996
1996
Test and testability techniques for open defects in RAM address decoders
  • M. Sachdev
  • Proceedings ED&TC European Design and Test…
  • 1996
  • Corpus ID: 870614
It is a prevalent assumption that all RAM address decoder defects can be modelled as RAM array faults influencing one or more RAM… 
1992
1992
An Architecture To Test Random Access Memories
  • R. Rajsuman
  • The Fifth International Conference on VLSI Design
  • 1992
  • Corpus ID: 33658623
1992
1992
A High Density Data Path Generator With Stretchable Cells
This paper describes a newly developed module generator for cell-based design which generates a data-path layout comparable to a… 
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