Skip to search formSkip to main contentSkip to account menu

Address decoder

In digital electronics, an address decoder is a binary decoder that has two or more inputs for address bits and one or more outputs for device… 
Wikipedia (opens in a new tab)

Related topics

Related topics

18 relations
Address busApplication-specific integrated circuitBinary decoderBus (computing)

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Review
2014
Review
2014
Design of Address Decoder and Sense Amplifier for SRAM
Address decoder and sense amplifier is important component of SRAM memory. Selection of storage cell and read operation is… 
2013
2013
Leakage Power Estimation & Minimization In a 6T SRAM Cell Using Dual Vth, Dual Tox, & Stacking Techniques
Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep… 
2013
2013
Design Techniques and Tradeoffs of FinFET SRAM Memories
........................................................................................................................................ iv List of Tables ............................................................................................................................... xii List of Figures ............................................................................................................................. xvi Chapter 
2009
2009
Long-run Uncertainty and Value
2008
2008
Detection of address decoder faults
The invention relates to detection of failure of an address decoder. A memory 2 is formed having an array of memory cells 4… 
2008
2008
New March Elements for Address Decoder Open and Resistive Open Fault Detection in SRAM Memories
This paper presents a complete analysis of the ability of March tests to detect ADOFs (Address Decoder Open Faults) and resistive… 
Review
2006
Review
2006
Design / Process Learning from Production Test
Modern Design-For-Test (DFT) practices not only simplify test generation but also make it much easier to diagnose problems… 
2004
2004
Built-In Self-Test Configurations for Atmel FPGAs Using Macro Generation Language
The development and automatic generation of Built-In Self-Test (BIST) configurations for Atmel AT40K series Field Programmable… 
2004
2004
FSRAM: Flexible Sequential and Random Access Memory for Embedded Systems
We propose a novel RAM architecture for embedded systems that allows both random-access and sequential access for reads and… 
1998
1998
Random pattern testability of memory address logic
  • J. Savir
  • IEEE Trans. Comput. Aided Des. Integr. Circuits…
  • 1998
  • Corpus ID: 33671733
An analytical method is described for determining the random pattern testability of faults in combinational logic feeding the…