Address decoder

In digital electronics, an address decoder is a binary decoder that has two or more inputs for address bits and one or more outputs for device… (More)
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Address busApplication-specific integrated circuitBinary decoderBus (computing)
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Papers overview

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2017
2017
Resistive Address Decoder
Hardwired dynamic NAND address decoders are widely used in random access memories to decode parts of the address. Replacing wires… (More)
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2014
2014
Novel design technique of address Decoder for SRAM
Address Decoder is an important digital block in SRAM which takes up to half of the total chip access time and significant part… (More)
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2010
2010
Low-Power FinFET design schemes for NOR address decoders
This paper presents and evaluates six novel, low-power, FinFET-based design schemes of the conventional NOR address decoder… (More)
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2009
2009
New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults
Due to the rapid decrease of technology feature size speed related faults, such as Address Decoder Delay Faults (ADDFs), are… (More)
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2008
2008
High-Performance Low-Power Selective Precharge Schemes for Address Decoders
Two novel address decoder schemes using selective precharging are presented and analyzed in this paper. These schemes, the AND… (More)
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2006
2006
Opens and Delay Faults in CMOS RAM Address Decoders
This paper presents a complete electrical analysis of address decoder delay faults "ADFs" caused by resistive opens in RAMs. A… (More)
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2002
2002
Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory
Multimedia applications are characterized by a largenumber of data accesses and complex array index manipulations.The built-in… (More)
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Highly Cited
2000
Highly Cited
2000
Point-to-point connectivity between neuromorphic chips using address events
I discuss connectivity between neuromorphic chips, which use the timing of fixed-height, fixed-width, pulses to encode… (More)
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2000
2000
Detection of Delay Faults in Memory Address Decoders
In this paper we present an efficient test concept for detection of delay faults in memory address decoders based on the march… (More)
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1998
1998
Address decoder faults and their tests for two-port memories
A two-port memory contains two duplicated sets of address decoders which operate independently. In this paper the effects of… (More)
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