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Address decoder

In digital electronics, an address decoder is a binary decoder that has two or more inputs for address bits and one or more outputs for device… 
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Related topics

Related topics

18 relations
Address busApplication-specific integrated circuitBinary decoderBus (computing)

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2008
2008
Detection of address decoder faults
The invention relates to detection of failure of an address decoder. A memory 2 is formed having an array of memory cells 4… 
2006
2006
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions
This paper presents a comparative analysis of ADOFs (Address Decoder Open Faults) and resistive-ADOFs in embedded-SRAMs. Such… 
2006
2006
VHDL Implementation of the Fast Wavelet Transform
In this paper, a VHDL implementation of a decomposition unit based on Mallat's fast Wavelet Transform, which utilizes a two… 
2006
2006
Low-leakage SRAM design with dual V/sub t/ transistors
This paper presents a method based on dual threshold voltage assignment to reduce the leakage power dissipation of SRAMs while… 
2004
2004
Built-In Self-Test Configurations for Atmel FPGAs Using Macro Generation Language
The development and automatic generation of Built-In Self-Test (BIST) configurations for Atmel AT40K series Field Programmable… 
2004
2004
FSRAM: Flexible Sequential and Random Access Memory for Embedded Systems
We propose a novel RAM architecture for embedded systems that allows both random-access and sequential access for reads and… 
2003
2003
Comparison of open and resistive-open defect test conditions in SRAM address decoders
This paper presents a comparative analysis of open (ADOF: Address Decoder Open Fault) and resistive open defects in address… 
1994
1994
Two-phase logic design by hardware flowcharts
Two-phase logic design is a technique that has long been used in the IC industry to increase data throughput and improve silicon… 
1992
1992
An Architecture To Test Random Access Memories
  • R. Rajsuman
  • The Fifth International Conference on VLSI Design
  • 1992
  • Corpus ID: 33658623
1992
1992
A High Density Data Path Generator With Stretchable Cells
This paper describes a newly developed module generator for cell-based design which generates a data-path layout comparable to a… 
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