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Address decoder

In digital electronics, an address decoder is a binary decoder that has two or more inputs for address bits and one or more outputs for device… 
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Related topics

Related topics

18 relations
Address busApplication-specific integrated circuitBinary decoderBus (computing)

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Optimal symbol misalignment estimation in asynchronous physical-layer network coding
In practical asynchronous physical-layer network coding (PNC) systems, the symbols from multiple transmitters to a common… 
2015
2015
Analog Digital Belief Propagation and its application to multi stage decoding systems
Next generation wireless systems will need to have higher spectral efficiency as the expected traffic volumes per unit bandwidth… 
2013
2013
A New March Test for Process-Variation Induced Delay Faults in SRAMs
Process variations are growing with technology scaling towards nano-scale. This brings new challenges to the design of memory… 
2011
2011
An Effective Test Algorithm and Diagnostic Implementation for Embedded Static Random Access Memories
An effective test algorithm and built-in self-test (BIST) with diagnostic support for embedded static random access memories… 
2006
2006
VHDL Implementation of the Fast Wavelet Transform
In this paper, a VHDL implementation of a decomposition unit based on Mallat's fast Wavelet Transform, which utilizes a two… 
2005
2005
Impact of stresses on the fault coverage of memory tests
Memory tests are applied in the industry using different algorithmic stresses (e.g., data-backgrounds) and non-algorithmic… 
2003
2003
Comparison of open and resistive-open defect test conditions in SRAM address decoders
This paper presents a comparative analysis of open (ADOF: Address Decoder Open Fault) and resistive open defects in address… 
1996
1996
Test and testability techniques for open defects in RAM address decoders
  • M. Sachdev
  • Proceedings ED&TC European Design and Test…
  • 1996
  • Corpus ID: 870614
It is a prevalent assumption that all RAM address decoder defects can be modelled as RAM array faults influencing one or more RAM… 
1992
1992
An Architecture To Test Random Access Memories
  • R. Rajsuman
  • The Fifth International Conference on VLSI Design
  • 1992
  • Corpus ID: 33658623
1992
1992
A High Density Data Path Generator With Stretchable Cells
This paper describes a newly developed module generator for cell-based design which generates a data-path layout comparable to a… 
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