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Address bus
An address bus is a computer bus (a series of lines connecting two or more devices) that is used to specify a physical address. When a processor or…
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Related topics
Related topics
50 relations
26-bit
48-bit
64-bit computing
Accelerated Graphics Port
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Application of TMS320VC5509A in Bluetooth Transmission
Lingyi Zhou
,
Ya-xia Liu
,
Sheng-Li Huang
2017
Corpus ID: 58911756
Bluetooth technology is the global wireless standard enabling the Internet of Things (IoT), it was created as an open standard to…
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2009
2009
IMMIGRANT MENTAL HEALTH POLICY BRIEF
N. Khanlou
2009
Corpus ID: 140906621
2007
2007
A Low Power Design of Gray and T 0 Codecs for the Address Bus Encoding for System Level Power Optimization
P. Saraswat
,
Ghazal Haghani
,
A. Bernard
2007
Corpus ID: 16197326
This report describes our attempt to design the Gray and T0 codecs to be used to encode the bits to be sent on the processor…
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2005
2005
A novel storage scheme for parallel turbo decoder
Xiang He
,
Han-wen Luo
,
Haibin Zhang
VTC--Fall. IEEE 62nd Vehicular Technology…
2005
Corpus ID: 19724166
In this paper we discuss a novel storage scheme for simultaneous memory access in parallel turbo decoder. The new scheme borrows…
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2005
2005
Low-Power Data Address Bus Encoding Method
Wei-Hao Chiao
,
Tsung-Hsi Weng
,
J. Shann
,
C. Chung
,
Jimmy Lu
ICCD
2005
Corpus ID: 6757563
Reducing power consumption of computer systems has gained much research attention recently. In a typical system, the memory bus…
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2002
2002
EZ encoding: a class of irredundant low power codes for data address and multiplexed address buses
Y. Aghaghiri
,
Massoud Pedram
,
F. Fallah
Proceedings Design, Automation and Test in…
2002
Corpus ID: 26589717
In this paper, we introduce a class of irredundant low power encoding techniques for memory address buses. For a data address bus…
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2002
2002
A Class of Irredundant Encoding Techniques for Reducing Bus Power
Y. Aghaghiri
,
F. Fallah
,
Massoud Pedram
J. Circuits Syst. Comput.
2002
Corpus ID: 13624443
This paper proposes a number of encoding techniques for decreasing power dissipation on global buses. The best target for these…
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1998
1998
Optical versus electronic bus for address-transactions in future SMP architectures
W. Hlayhel
,
D. Litaize
,
L. Fesquet
,
J. Collet
Proceedings. International Conference on…
1998
Corpus ID: 17206320
The fast evolution of processor performance necessitates a permanent evolution of all the multiprocessor components, even for…
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Highly Cited
1996
Highly Cited
1996
Thumb: reducing the cost of 32-bit RISC performance in portable and consumer applications
L. Goudge
,
S. Segars
COMPCON '96. Technologies for the Information…
1996
Corpus ID: 206568018
This article discusses a RISC architectural innovation from ARM known as Thumb. High-end embedded control applications such as…
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1994
1994
Reducing Power Consumption at the Control Path of High Performance Microprocessors
Ching-Long Su
,
C. Tsui
,
A. Despain
1994
Corpus ID: 12596927
Low power embedded processors become more important for portable applications. For CMOS circuits, power is consumed during the…
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