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Address bus
An address bus is a computer bus (a series of lines connecting two or more devices) that is used to specify a physical address. When a processor or…
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50 relations
26-bit
48-bit
64-bit computing
Accelerated Graphics Port
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Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2019
Highly Cited
2019
An Off-Chip Attack on Hardware Enclaves via the Memory Bus
Dayeol Lee
,
D. Jung
,
Ian T. Fang
,
Chia-che Tsai
,
Raluca A. Popa
USENIX Security Symposium
2019
Corpus ID: 208617341
This paper shows how an attacker can break the confidentiality of a hardware enclave with Membuster, an off-chip attack based on…
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2017
2017
Verification of Power-Management Specification at Early Stages of Power-Constrained Systems Design
Dominik Macko
,
K. Jelemenská
,
P. Cicák
J. Circuits Syst. Comput.
2017
Corpus ID: 207120415
Nowadays, power is a dominant factor that constrains highly integrated hardware-systems designs. The implied problems of high…
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2002
2002
ALBORZ: Address Level Bus Power Optimization
Y. Aghaghiri
,
F. Fallah
,
Massoud Pedram
Proceedings International Symposium on Quality…
2002
Corpus ID: 11582186
In this paper we introduce a new low power address bus encoding technique, and the resulting code, named ALBORZ. The ALBORZ code…
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Highly Cited
1999
Highly Cited
1999
Low-power memory mapping through reducing address bus activity
P. Panda
,
N. Dutt
IEEE Transactions on Very Large Scale Integration…
1999
Corpus ID: 15013308
Arrays in behavioral specifications that are too large to fit into on-chip registers are usually mapped to off-chip memories…
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Highly Cited
1998
Highly Cited
1998
Power optimization of core-based systems by address bus encoding
L. Benini
,
G. Micheli
,
E. Macii
,
M. Poncino
,
S. Quer
IEEE Transactions on Very Large Scale Integration…
1998
Corpus ID: 16936299
This paper presents a solution to the problem of reducing the power dissipated by a digital system containing an intellectual…
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Highly Cited
1998
Highly Cited
1998
Address bus encoding techniques for system-level power optimization
L. Benini
,
G. Micheli
,
D. Sciuto
,
E. Macii
,
C. Silvano
Proceedings Design, Automation and Test in Europe
1998
Corpus ID: 5048685
The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore…
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Highly Cited
1997
Highly Cited
1997
Exploiting the locality of memory references to reduce the address bus energy
E. Musoll
,
T. Lang
,
J. Cortadella
Proceedings / International Symposium on Low…
1997
Corpus ID: 15255303
The energy consumption at the I/O pins is a significant part of the overall chip consumption. This paper presents a method for…
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Highly Cited
1997
Highly Cited
1997
Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems
L. Benini
,
G. Micheli
,
E. Macii
,
D. Sciuto
,
C. Silvano
Proceedings Great Lakes Symposium on VLSI
1997
Corpus ID: 206694849
In microprocessor-based systems, large power savings can be achieved through reduction of the transition activity of the on- and…
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Highly Cited
1996
Highly Cited
1996
Thumb: reducing the cost of 32-bit RISC performance in portable and consumer applications
L. Goudge
,
S. Segars
COMPCON '96. Technologies for the Information…
1996
Corpus ID: 206568018
This article discusses a RISC architectural innovation from ARM known as Thumb. High-end embedded control applications such as…
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1996
1996
Reducing address bus transition for low power memory mapping
P. Panda
,
N. Dutt
Proceedings ED&TC European Design and Test…
1996
Corpus ID: 12473373
We present low power techniques for mapping arrays in behavioral specifications to physical memory, specifically for memory…
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