• Publications
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The MOLEN polymorphic processor
TLDR
A microarchitecture based on reconfigurable hardware emulation to allow high-speed reconfiguration and execution of the processor and to prove the viability of the proposal, the proposal was experimented with the MPEG-2 encoder and decoder and a Xilinx Virtex II Pro FPGA.
64-bit floating-point FPGA matrix multiplication
TLDR
A 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations and implement a scalable linear array of processing elements (PE) supporting the proposed algorithm in the Xilinx Virtex II Pro technology.
Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array
TLDR
An architectural exploration methodology and its results for the first implementation of the ADRES architecture on a 90nm standard-cell technology are presented and an optimized architecture is derived.
Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array
TLDR
This paper investigates the influence of register file partitions, register file sizes and the interconnection topology of ADRES, and proposes an enhanced architecture instantiation that improves performance by 60 - 70% and reduces energy by 50%.
March LR: a test for realistic linked faults
TLDR
An overview of the most important and commonly used fault models, including the industry's popular disturb fault model, are given and a methodology to design tests for realistic linked faults is presented, resulting in the new tests March LR, March LRD and March LRDD.
A novel fast online placement algorithm on 2D partially reconfigurable devices
TLDR
This paper proposes a new strategy for online placement algorithm on 2D partially reconfigurable devices, termed the Quad-Corner (QC), which achieves better placement quality and fast online placement compared to existing approaches.
Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications
TLDR
A Binary Translation algorithm implemented in hardware, which works in parallel to a MIPS processor, responsible for transforming sequences of instructions at runtime to be executed on a dynamic coarse-grain reconfigurable array, supporting speculative execution.
DWARV: Delftworkbench Automated Reconfigurable VHDL Generator
TLDR
The carried experiments on the MOLEN polymorphic processor prototype suggest overall application speedups between 1.4x and 6.8x, corresponding to 13% to 94% of the theoretically achievable maximums, constituted by Amdahl's law.
A Platform for RFID Security and Privacy Administration (Awarded Best Paper!)
TLDR
The RFID Guardian is presented, the first-ever unified platform for RFID security and privacy administration, and offers a glimpse of what system administration may be like in the future, when laymen face the responsibility to manage systems of tiny computers that they are barely aware of.
Multimedia rectangularly addressable memory
TLDR
A scalable data alignment scheme incorporating module assignment functions and a generic addressing function for parallel access of randomly aligned rectangular blocks of data is proposed and speedups close to 8/spl times/ can be expected when compared to linear addressing schemes.
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