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Low power design methodologies
Preface. 1. Introduction J.M. Rabaey, et al. Part I: Technology and circuit design levels. 2. Device and technology impact on low power electronics Chenming Hu. 3. Low power circuit technologies C.Expand
Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits
TLDR
Circuit optimization and design automation techniques are introduced to bring leakage under control in CMOS circuits and present techniques for active leakage control. Expand
Minimizing data center cooling and server power costs
TLDR
The resulting optimization problem is formulated as an Integer Linear Programming problem and a heuristic algorithm that solves it in polynomial time is presented, showing an average of 13% power saving for different data center utilization rates. Expand
Leakage current reduction in CMOS VLSI circuits by input vector control
TLDR
Two runtime mechanisms for reducing the leakage current of a CMOS circuit are described and a design technique for applying the minimum leakage input to a sequential circuit is presented, which shows that it is possible to reduce the leakage by an average of 25% with practically no delay penalty. Expand
Power minimization in IC design: principles and applications
TLDR
An in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems is presented and the many issues facing designers at architectural, logical, and physical levels of design abstraction are described. Expand
Power punch: Towards non-blocking power-gating of NoC routers
TLDR
Two mechanisms are proposed that not only allow power control signals to utilizing existing slack at source nodes to wake up powered-off routers along the first few hops before packets are injected, but also allow these signals to utilize hop count slack by staying ahead of packets to "punch through " any blocked routers alongThe imminent path of packets. Expand
Probabilistic error propagation in logic circuits using the Boolean difference calculus
A gate level probabilistic error propagation model is presented which takes as input the Boolean function of the gate, the signal and error probabilities of the gate inputs, and the gate errorExpand
Energy Minimization Using Multiple Supply Voltages
TLDR
Experimental results show that using four supply voltage levels on a number of standard benchmarks, an average energy saving of 53% can be obtained compared to using one fixed supply voltage level. Expand
Dynamic voltage and frequency scaling based on workload decomposition
TLDR
Measurements show that, for a number of widely used software applications, a CPU energy saving of 80% can be achieved for memory-bound programs while satisfying the user-specified timing constraints. Expand
Power-aware source routing protocol for mobile ad hoc networks
TLDR
Simulation results show that the proposed power-aware source routing protocol has a higher performance than other source initiated routing protocols in terms of the network lifetime. Expand
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