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Low power design methodologies
Preface. 1. Introduction J.M. Rabaey, et al. Part I: Technology and circuit design levels. 2. Device and technology impact on low power electronics Chenming Hu. 3. Low power circuit technologies C.Expand
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Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits
In many new high performance designs, the leakage component of power consumption is comparable to the switching component. Reports indicate that 40% or even higher percentage of the total powerExpand
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Minimizing data center cooling and server power costs
This paper focuses on power minimization in a data center accounting for both the information technology equipment and the air conditioning power usage. In particular we address the serverExpand
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Energy Minimization Using Multiple Supply Voltages
We present a dynamic programming technique for solving the multiple supply voltage scheduling problem in both non-pipelined and functionally pipelined data-paths. The scheduling problem refers to theExpand
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Power minimization in IC design: principles and applications
Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance andExpand
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Power punch: Towards non-blocking power-gating of NoC routers
As chip designs penetrate further into the dark silicon era, innovative techniques are much needed to power off idle or under-utilized system components while having minimal impact on performance.Expand
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Leakage current reduction in CMOS VLSI circuits by input vector control
The first part of this paper describes two runtime mechanisms for reducing the leakage current of a CMOS circuit. In both cases, it is assumed that the system or environment produces a "sleep" signalExpand
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Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times
This work presents an intraprocess dynamic voltage and frequency scaling (DVFS) technique targeted toward nonreal-time applications running on an embedded system platform. The key idea is to make useExpand
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Probabilistic error propagation in logic circuits using the Boolean difference calculus
A gate level probabilistic error propagation model is presented which takes as input the Boolean function of the gate, the signal and error probabilities of the gate inputs, and the gate errorExpand
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Dynamic voltage and frequency scaling based on workload decomposition
This paper presents a technique called "workload decomposition" in which the CPU workload is decomposed in two parts: on-chip and off-chip. The on-chip workload signifies the CPU clock cycles thatExpand
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