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64-bit computing
Known as:
LP64
, Native x86-64 Windows software
, 64-bit OS
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In computer architecture, 64-bit computing is the use of processors that have datapath widths, integer size, and memory address widths of 64 bits…
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Related topics
Related topics
50 relations
3 GB barrier
32-bit
ARM architecture
Address space
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2007
2007
Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology
Weiwu Hu
,
Ji-Ye Zhao
,
Shi-Qiang Zhong
,
Xu Yang
,
E. Guidetti
,
Chris Wu
Journal of Computational Science and Technology
2007
Corpus ID: 24776532
This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue…
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2003
2003
Low power multiplication algorithm for switching activity reduction through operand decomposition
Masayuki Ito
,
D. Chinnery
,
K. Keutzer
Proceedings 21st International Conference on…
2003
Corpus ID: 11611919
A novel low power multiplication algorithm for reducing switching activity through operand decomposition is proposed. Our…
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2000
2000
Cryptanalysis of Alleged A 5 Stream Cipher
W. Chambers
,
Walter Fumy Ed
,
J. Golic
2000
Corpus ID: 14474901
A binary stream cipher, known as A5, consisting of three short LFSRs of total length 64 that are mutually clocked in the stop/go…
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1999
1999
Series approximation methods for divide and square root in the Power3/sup TM/ processor
M. Schmookler
,
R. Agarwal
,
F. Gustavson
Proceedings 14th IEEE Symposium on Computer…
1999
Corpus ID: 15674943
The Power3 processor is a 64-bit implementation of the PowerPC/sup TM/ architecture and is the successor to the Power2/sup TM…
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1999
1999
TriMedia CPU64 application domain and benchmark suite
A. K. Riemens
,
K. Vissers
,
R. Schutten
,
G. Hekstra
,
G. L. Hei
,
F. Sijstermans
Proceedings IEEE International Conference on…
1999
Corpus ID: 14697828
At Philips Research Labs, we are investigating the 64-bit VLIW core (also called CPU64) for future TriMedia processors. This…
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Highly Cited
1995
Highly Cited
1995
The PowerPC 620 microprocessor: a high performance superscalar RISC microprocessor
D. Levitan
,
T. Thomas
,
P. Tu
Digest of Papers. COMPCON'95. Technologies for…
1995
Corpus ID: 33953182
The PowerPC 620 RISC microprocessor is the first chip for the application server and technical workstation product line within…
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1995
1995
Internal architecture of Alpha 21164 microprocessor
P. Bannon
,
J. Keller
Digest of Papers. COMPCON'95. Technologies for…
1995
Corpus ID: 206567870
The internal architecture of a 1200 MIPS/600 MFLOPS (peak) high-performance CMOS ALPHA microprocessor chip is described. This…
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1995
1995
Microarchitecture of HaL's CPU
N. Patkar
,
A. Katsuno
,
+6 authors
D. Tovey
Digest of Papers. COMPCON'95. Technologies for…
1995
Corpus ID: 37378617
The HaL PM1 CPU is the first implementation of the 64-bit SPARC Version 9 instruction set architecture. The processor utilizes…
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1994
1994
Architecture of a 64-bit fuzzy inference processor
A. Ungering
,
Karl Goser
Proceedings of IEEE 3rd International Fuzzy…
1994
Corpus ID: 62652300
The architecture of a 64-bit fuzzy inference processor (FIP) will be presented. A fuzzy system consisting of the FIP and a 64-bit…
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Review
1993
Review
1993
Overview of the CHIP Compiler System
A. Aggoun
,
N. Beldiceanu
Workshop on Constraint Logic Programming
1993
Corpus ID: 27206835
The MIPSpro compiler system consists of a set of components that enable you to create new 32-bit and 64-bit executable programs…
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