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64-bit computing
Known as:
LP64
, Native x86-64 Windows software
, 64-bit OS
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In computer architecture, 64-bit computing is the use of processors that have datapath widths, integer size, and memory address widths of 64 bits…
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Related topics
Related topics
50 relations
3 GB barrier
32-bit
ARM architecture
Address space
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2012
2012
Cryptanalysis of mCrypton—A lightweight block cipher for security of RFID tags and sensors
H. Mala
,
Mohammad Dakhilalian
,
Mohsen Shakiba
International Journal of Communication Systems
2012
Corpus ID: 7075409
mCrypton is a 64‐bit lightweight block cipher designed for use in low‐cost and resource‐constrained applications such as RFID…
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Highly Cited
2007
Highly Cited
2007
Efficient Handling of N-gram Language Models for Statistical Machine Translation
Marcello Federico
,
M. Cettolo
WMT@ACL
2007
Corpus ID: 603858
Statistical machine translation, as well as other areas of human language processing, have recently pushed toward the use of…
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Highly Cited
2007
Highly Cited
2007
A mux-based High-Performance Single-Cycle CMOS Comparator
H. Lam
,
C. Tsui
IEEE Transactions on Circuits and Systems - II…
2007
Corpus ID: 20172844
In this brief, a new architecture for high-fan-in CMOS comparator is proposed. The architecture is based on a hierarchical two…
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Highly Cited
2005
Highly Cited
2005
Data Encryption Standard (DES)
A. Biryukov
,
C. Cannière
Encyclopedia of Cryptography and Security
2005
Corpus ID: 6547274
Background TheData Encryption Standard (DES) [] has been around for more than years. During this time, the standard was…
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Highly Cited
2003
Highly Cited
2003
Testing parallel random number generators
A. Srinivasan
,
M. Mascagni
,
D. Ceperley
Parallel Computing
2003
Corpus ID: 15627466
Highly Cited
2003
Highly Cited
2003
Energy-delay estimation technique for high-performance microprocessor VLSI adders
V. Oklobdzija
,
B. Zeydel
,
H. Dao
,
S. Mathew
,
R. Krishnamurthy
Proceedings 16th IEEE Symposium on Computer…
2003
Corpus ID: 331394
We motivate the concept of comparing VLSI adders based on their energy-delay trade-offs and present a technique for estimating…
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2000
2000
Increasing relevance of memory hardware errors: a case for recoverable programming models
D. Milojicic
,
A. Messer
,
J. Shau
,
G. Fu
,
Alberto Muñoz
ACM SIGOPS European Workshop
2000
Corpus ID: 12573765
It is a common belief that most of computer system failures nowadays stem from programming errors. Computer systems are becoming…
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Highly Cited
1999
Highly Cited
1999
Experimenting with Shared Generation of RSA Keys
Michael Malkin
,
Thomas D. Wu
,
D. Boneh
Network and Distributed System Security Symposium
1999
Corpus ID: 11088284
We describe an implementation of a distributed algorithm to generate a shared RSA key. At the end of the computation, an RSA…
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Highly Cited
1998
Highly Cited
1998
1 GHz 64-bit high-speed comparator using ANT dynamic logic with two-phase clocking
Chua-Chin Wang
,
Chung-Yu Wu
,
Kun-Chu Tsai
1998
Corpus ID: 61525670
A high-speed 64-bit comparator using two-phase clocking dynamic CMOS logic with modified noninverting all-N-transistor block is…
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Highly Cited
1995
Highly Cited
1995
UltraSPARC: the next generation superscalar 64-bit SPARC
D. Greenley
,
J. Bauman
,
+26 authors
G. Zyner
Digest of Papers. COMPCON'95. Technologies for…
1995
Corpus ID: 2254629
UltraSPARC is the first microprocessor from Sun Microsystems' SPARC Technology Business to implement the new 64-bit SPARC V9…
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