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32-bit
Known as:
32 bit microprocessor
, 32 bits
, 32-bit CPU
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In computer architecture, 32-bit integers, memory addresses, or other data units are those that are at most 32 bits (4 octets) wide. Also, 32-bit CPU…
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50 relations
"Classic" Mac OS
ARM Cortex-A9
Accelerated Graphics Port
Android
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
An Application-Specific Forecasting Algorithm for Extending WSN Lifetime
Femi A. Aderohunmu
,
Giacomo Paci
,
D. Brunelli
,
Jeremiah D. Deng
,
L. Benini
,
M. Purvis
IEEE International Conference on Distributed…
2013
Corpus ID: 10829412
Data reduction strategy is one of the schemes employed to extend network lifetime. In this paper we present an implementation of…
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Highly Cited
2011
Highly Cited
2011
Accelerating Regular LDPC Code Decoders on GPUs
Cheng-Chun Chang
,
Yang-Lang Chang
,
Min-Yu Huang
,
Bormin Huang
IEEE Journal of Selected Topics in Applied Earth…
2011
Corpus ID: 495344
Modern active and passive satellite and airborne sensors with higher temporal, spectral and spatial resolutions for Earth remote…
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Highly Cited
2010
Highly Cited
2010
Combating Aging with the Colt Duty Cycle Equalizer
Erika Gunadi
,
Abhishek A. Sinkar
,
N. Kim
,
Mikko H. Lipasti
Micro
2010
Corpus ID: 16902486
Bias temperature instability, hot-carrier injection, and gate-oxide wear out will cause severe lifetime degradation in the…
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Highly Cited
2007
Highly Cited
2007
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration
Christopher Claus
,
Florian Helmut Müller
,
J. Zeppenfeld
,
W. Stechele
IEEE International Parallel and Distributed…
2007
Corpus ID: 8617311
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial…
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Highly Cited
2007
Highly Cited
2007
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
Martin Thuresson
,
Magnus Själander
,
Magnus Björk
,
L. Svensson
,
P. Larsson-Edefors
,
P. Stenström
International Conference on Embedded Computer…
2007
Corpus ID: 9954879
We introduce FlexCore, the first exemplar of an architecture based on the FlexSoC framework. Comprising the same datapath units…
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Review
2006
Review
2006
PAC DSP Core and Application Processors
David Chih-Wei Chang
,
I-Tao Liao
,
Jenq Kuen Lee
,
Wen-Feng Chen
,
S. Tseng
,
C. Jen
IEEE International Conference on Multimedia and…
2006
Corpus ID: 8029106
This paper provides an overview of the parallel architecture core (PAC) project led by SoC Technology Center of Industrial…
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Highly Cited
2005
Highly Cited
2005
Data Encryption Standard (DES)
A. Biryukov
,
C. Cannière
Encyclopedia of Cryptography and Security
2005
Corpus ID: 6547274
Background TheData Encryption Standard (DES) [] has been around for more than years. During this time, the standard was…
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Highly Cited
2003
Highly Cited
2003
Testing parallel random number generators
A. Srinivasan
,
M. Mascagni
,
D. Ceperley
Parallel Computing
2003
Corpus ID: 15627466
Review
1983
Review
1983
CEDAR: a large scale multiprocessor
D. Gajski
,
D. Kuck
,
D. Lawrie
,
A. Sameh
CARN
1983
Corpus ID: 2361679
This paper presents an overview of Cedar, a large scale multiprocessor being designed at the University of Illinois. This machine…
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1983
1983
The 8 by 8 display
R. Sproull
,
I. Sutherland
,
A. Thomson
,
S. Gupta
,
C. Minter
TOGS
1983
Corpus ID: 14642137
This paper describes a display system designed to make the recording and rearrangement of bits in a frame-buffer display system…
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