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32-bit

Known as: 32 bit microprocessor, 32 bits, 32-bit CPU 
In computer architecture, 32-bit integers, memory addresses, or other data units are those that are at most 32 bits (4 octets) wide. Also, 32-bit CPU… 
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"Classic" Mac OSARM Cortex-A9Accelerated Graphics PortAndroid

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
An Application-Specific Forecasting Algorithm for Extending WSN Lifetime
Data reduction strategy is one of the schemes employed to extend network lifetime. In this paper we present an implementation of… 
Highly Cited
2011
Highly Cited
2011
Accelerating Regular LDPC Code Decoders on GPUs
Modern active and passive satellite and airborne sensors with higher temporal, spectral and spatial resolutions for Earth remote… 
Highly Cited
2010
Highly Cited
2010
Combating Aging with the Colt Duty Cycle Equalizer
Bias temperature instability, hot-carrier injection, and gate-oxide wear out will cause severe lifetime degradation in the… 
2008
2008
A coarse-grain reconfigurable architecture for multimedia applications featuring subword computation capabilities
This paper presents the design and the implementation of a coarse-grain reconfigurable machine used as an accelerator for a… 
Highly Cited
2007
Highly Cited
2007
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial… 
2007
2007
An FPGA-based architecture for a local tone-mapping operator
This paper presents an FPGA-based architecture for local tone mapping of gray scale high dynamic range images. The architecture… 
Review
2006
Review
2006
PAC DSP Core and Application Processors
This paper provides an overview of the parallel architecture core (PAC) project led by SoC Technology Center of Industrial… 
Highly Cited
2005
Highly Cited
2005
Data Encryption Standard (DES)
Background TheData Encryption Standard (DES) [] has been around for more than  years. During this time, the standard was… 
2005
2005
IEEE 802 . 11 Rate Control Algorithms : Experimentation and Performance Evaluation in Infrastructure Mode
This paper evaluates the performance of practical Rate Control Algorithms (RCAs) operating at the Media Access Control (MAC… 
Review
1983
Review
1983
CEDAR: a large scale multiprocessor
This paper presents an overview of Cedar, a large scale multiprocessor being designed at the University of Illinois. This machine… 
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