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32-bit
Known as:
32 bit microprocessor
, 32 bits
, 32-bit CPU
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In computer architecture, 32-bit integers, memory addresses, or other data units are those that are at most 32 bits (4 octets) wide. Also, 32-bit CPU…
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50 relations
"Classic" Mac OS
ARM Cortex-A9
Accelerated Graphics Port
Android
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
An Application-Specific Forecasting Algorithm for Extending WSN Lifetime
Femi A. Aderohunmu
,
Giacomo Paci
,
Davide Brunelli
,
Jeremiah D. Deng
,
L. Benini
,
M. Purvis
IEEE International Conference on Distributed…
2013
Corpus ID: 10829412
Data reduction strategy is one of the schemes employed to extend network lifetime. In this paper we present an implementation of…
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2010
2010
LEON3 ViP: A Virtual Platform with Fault Injection Capabilities
Antônio da Silva
,
Sebastián Sánchez
13th Euromicro Conference on Digital System…
2010
Corpus ID: 16962465
In addition to functional simulation for validation of hardware/software designs, there are additional robustness requirements…
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Highly Cited
2007
Highly Cited
2007
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration
Christopher Claus
,
Florian Helmut Müller
,
J. Zeppenfeld
,
W. Stechele
IEEE International Parallel and Distributed…
2007
Corpus ID: 8617311
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial…
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2007
2007
Hardware implementation of an SAD based stereo vision algorithm
K. Ambrosch
,
W. Kubinger
,
M. Humenberger
,
A. Steininger
IEEE Conference on Computer Vision and Pattern…
2007
Corpus ID: 15021884
This paper presents the hardware implementation of a stereo vision core algorithm, that runs in real-time and is targeted at…
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2007
2007
A Block Cipher based PRNG Secure Against Side-Channel Key Recovery
C. Petit
,
F. Standaert
,
Olivier Pereira
,
Tal Malkin
,
M. Yung
IACR Cryptology ePrint Archive
2007
Corpus ID: 12852565
We study the security of a block cipher-based pseudorandom number generator, both in the black box world and in the physical…
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2002
2002
A Brute-Force Approach to Automatic Induction of Machine Code on CISC Architectures
European Conference on Genetic Programming
2002
Corpus ID: 28464525
The usual approach to address the brittleness of machine code in evolution is to constrain mutation and crossover to ensure…
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Highly Cited
1996
Highly Cited
1996
Thumb: reducing the cost of 32-bit RISC performance in portable and consumer applications
L. Goudge
,
S. Segars
COMPCON '96. Technologies for the Information…
1996
Corpus ID: 206568018
This article discusses a RISC architectural innovation from ARM known as Thumb. High-end embedded control applications such as…
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1990
1990
The Gmicro/300 32-bit microprocessor
T. Kitahara
,
Taizo Satoh
IEEE Micro
1990
Corpus ID: 12948736
A high-end microprocessor, the Gmicro/300, based on the TRON architecture specification is described. In contrast to other RISC…
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1987
1987
A 32-bit CMOS microprocessor with on-chip cache and TLB
H. Kadota
,
J. Miyake
,
+4 authors
K. Kagawa
1987
Corpus ID: 62718339
A 32-b general-purpose microprocessor has been developed using 1-/spl mu/m CMOS technology. The chip, containing 372 K…
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Review
1985
Review
1985
A 32-bit VLSI digital signal processor
W. P. Hayes
,
R. N. Kershaw
,
+13 authors
L. Tran
IEEE Journal of Solid-State Circuits
1985
Corpus ID: 26850550
A general-purpose programmable digital signal processor (DSP) has been implemented in 1.5-/spl mu/m (L/SUB eff/) NMOS technology…
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