Christopher Claus

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The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconf iguration, also known as dynamic partial reconf iguration (DPR). Taking this concept one step further, partial dynamic self-reconf iguration becomes possible through the Internal Conf iguration Access Port (ICAP). In this paper a framework for lowering reconf iguration(More)
Hardware/software partitioning of algorithms is gaining more and more importance in order to benefit from the advantages of both worlds. Pure software implementations are easy to change but the processing time is rather high. By contrast pure hardware implementations usually result in faster processing due to inherent parallelism but they do not offer the(More)
In this paper we show a reconfigurable hardware architecture for the acceleration of video-based driver assistance applications in future automotive systems. The concept is based on a separation of pixel-level operations and high level application code. Pixel-level operations are accelerated by coprocessors, whereas high level application code is(More)
Today's FPGAs (Field Programmable Gate Arrays) are widely used, but not to their full potential. In Virtex series FPGAs from Xilinx a special feature, the dynamic and partial reconfiguration is available. This feature enables a designer to create a system on chip with a static area and a reconfigurable part that can be exchanged during run-time while the(More)
Using Field Programmable Gate Arrays (FPGAs) as accelerators for image or video processing operations and algorithms has gained increasing attention over the last few years. One reason for that is FPGAs are able to exploit both temporal and spatial parallelism. In this paper two platforms for FPGA-based real-time image and video processing are presented and(More)