Networks on Chips: A New SoC Paradigm
Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies.
A survey of design techniques for system-level dynamic power management
- L. Benini, A. Bogliolo, G. Micheli
- Computer ScienceIEEE Transactions on Very Large Scale Integration…
- 1 June 2000
This paper describes how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption, and survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components.
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
- D. Bertozzi, A. Jalabert, G. Micheli
- Computer ScienceIEEE Transactions on Parallel and Distributed…
- 1 February 2005
This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler).
Policy optimization for dynamic power management
- L. Benini, A. Bogliolo, Giuseppe A. Paleologo, G. Micheli
- Computer ScienceProceedings Design and Automation Conference…
- 1 May 1998
It is shown that the fundamental problem of finding an optimal policy which maximizes the average performance level of a system, subject to a constraint on the power consumption, can be formulated as a stochastic optimization problem called policy optimization.
Analysis of error recovery schemes for networks on chips
- S. Murali, T. Theocharides, N. Vijaykrishnan, M. Irwin, L. Benini, G. Micheli
- Computer ScienceIEEE Design & Test of Computers
- 1 September 2005
This article explores error control mechanisms at the data link and network layers and presents the schemes' architectural details to investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms.
Soft-to-Hard Vector Quantization for End-to-End Learning Compressible Representations
We present a new approach to learn compressible representations in deep architectures with an end-to-end training strategy. Our method is based on a soft (continuous) relaxation of quantization and…
Networks on chips - technology and tools
This book is the first to provide a unified overview of NoC technology, and includes in-depth analysis of all the on-chip communication challenges, from physical wiring implementation up to software architecture, and a complete classification of their various Network-on-Chip approaches and solutions.
Hibernus: Sustaining Computation During Intermittent Supply for Energy-Harvesting Systems
- Domenico Balsamo, A. Weddell, G. Merrett, B. Al-Hashimi, D. Brunelli, L. Benini
- Computer ScienceIEEE Embedded Systems Letters
- 1 March 2015
A new approach, Hibernus, is proposed, which enables computation to be sustained during intermittent supply by reactively hibernating: saving system state only once, when power is about to be lost, and then sleeping until the supply recovers.
Xpipes: a network-on-chip architecture for gigascale systems-on-chip
An advanced NoC architecture, called Xpipes, targeting high performance and reliable communication for on-chip multi-processors is introduced, which consists of a library of soft macros that are design-time composable and tunable so that domain-specific heterogeneous architectures can be instantiated and synthesized.
Dynamic power management - design techniques and CAD tools
Different approaches are presented and organized in an order related to their applicability to control-units, macro-blocks, digital circuits and electronic systems, respectively based on the principle of exploiting idleness of circuits, systems, or portions thereof.