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Networks on Chips: A New SoC Paradigm
On-chip micronetworks, designed with a layered methodology, will meet the distinctive challenges of providing functionally correct, reliable operation of interacting system-on-chip components. AExpand
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A survey of design techniques for system-level dynamic power management
Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or aExpand
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NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
The growing complexity of customizable single-chip multiprocessors is requiring communication resources that can only be provided by a highly-scalable communication infrastructure. This trend isExpand
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Analysis of error recovery schemes for networks on chips
In this article, we discuss design constraints to characterize efficient error recovery mechanisms for the NoC design environment. We explore error control mechanisms at the data link and networkExpand
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Xpipes: a network-on-chip architecture for gigascale systems-on-chip
The growing complexity of embedded multiprocessor architectures for digital media processing will soon require highly scalable communication infrastructures. Packet switched networks-on-chip (NoC)Expand
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Networks on chips - technology and tools
The design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chipsExpand
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Error control schemes for on-chip communication links: the energy-reliability tradeoff
On-chip interconnection networks for future systems on chip (SoC) will have to deal with the increasing sensitivity of global wires to noise sources such as crosstalk or power supply noise. Hence,Expand
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Hibernus: Sustaining Computation During Intermittent Supply for Energy-Harvesting Systems
A key challenge to the future of energy-harvesting systems is the discontinuous power supply that is often generated. We propose a new approach, Hibernus, which enables computation to be sustainedExpand
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Platform 2012, a many-core computing accelerator for embedded SoCs: Performance evaluation of visual analytics applications
P2012 is an area- and power-efficient many-core computing accelerator based on multiple globally asynchronous, locally synchronous processor clusters. Each cluster features up to 16 processors withExpand
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Policy optimization for dynamic power management
Dynamic power management schemes (also called policies) reduce the power consumption of complex electronic systems by trading off performance for power in a controlled fashion, taking system workloadExpand
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