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A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks (extended version)
TLDR
The fair evaluation and comparison of side-channel attacks and countermeasures has been a long standing open question, limiting further developments in the field. Expand
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The Swiss-Knife RFID Distance Bounding Protocol
TLDR
We propose an RFID authentication protocol that combines all the expected properties at the same time: it resists against both mafia fraud and terrorist attacks. Expand
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SEA: A Scalable Encryption Algorithm for Small Embedded Applications
TLDR
We propose low-cost encryption routines (i.e. with small code size and memory) targeted for processors with a limited instruction set. Expand
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Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications
TLDR
We propose an efficient solution to combine Rijndael encryption and decryption in one FPGA design, with a strong focus on low area constraints. Expand
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Template Attacks in Principal Subspaces
TLDR
We propose a probabilistic side-channel attack in the principal subspace of the traces. Expand
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On the Energy Cost of Communication and Cryptography in Wireless Sensor Networks
TLDR
We investigate the energy cost of cryptographic protocols, both from a communication and a computation point of view, based on practical measurements on the MICAz and TelosB sensors. Expand
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Univariate side channel attacks and leakage modeling
TLDR
Differential power analysis is a powerful cryptanalytic technique that exploits information leaking from physical implementations of cryptographic algorithms. Expand
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Algebraic Side-Channel Attacks on the AES: Why Time also Matters in DPA
TLDR
In this paper, we investigate the extent to which they can be exploited against the AES Rijndael in an 8-bit controller and discuss their practical specificities. Expand
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Implementation of the AES-128 on Virtex-5 FPGAs
TLDR
This paper presents an updated implementation of the Advanced Encryption Standard (AES) on the recent Xilinx Virtex-5 FPGAs. Expand
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LS-Designs: Bitslice Encryption for Efficient Masked Software Implementations
TLDR
In this paper, we study possible optimizations when specializing the designs to Boolean masking in a principled manner. Expand
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