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Circuit extraction
Known as:
Layout extraction
, Netlist extraction
The electric circuit extraction or simply circuit extraction, also netlist extraction, is the translation of an integrated circuit layout back into…
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Related topics
Related topics
12 relations
Electromagnetic field solver
Electronic design automation
Formal equivalence checking
Integrated circuit layout
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Broader (1)
Electronic engineering
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2012
2012
A Compact Dual-Band EMI Metasurface Shield With an Actively Tunable Polarized Lower Band
M. M. Masud
,
B. Ijaz
,
I. Ullah
,
B. Braaten
IEEE transactions on electromagnetic…
2012
Corpus ID: 12865734
In this letter, a compact tunable metasurface for dual-band electromagnetic interference (EMI) shielding is being proposed. In…
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2009
2009
Verifying equivalence of memories using a first order logic theorem prover
Z. Khasidashvili
,
Mahmoud Kinanah
,
A. Voronkov
Formal Methods in Computer-Aided Design
2009
Corpus ID: 6907276
We propose a new method for equivalence checking of RTL and schematic descriptions of memories using translation into first-order…
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2007
2007
Efficient De-Embedding Technique for 110-GHz Deep-Channel-MOSFET Characterization
C. Andrei
,
D. Gloria
,
F. Danneville
,
G. Dambrine
IEEE Microwave and Wireless Components Letters
2007
Corpus ID: 34074374
In this letter, a de-embedding procedure is proposed to accurately extract the small signal equivalent circuit of advanced…
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2005
2005
Power analysis of rotary clock
Zhengtao Yu
,
Xun Liu
IEEE Computer Society Annual Symposium on VLSI
2005
Corpus ID: 15191753
Rotary clock is a multi-gigahertz clock distribution technique based on the principle of wave propagation in transmission lines…
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2003
2003
On-chip interconnect-aware design and modeling methodology based on high bandwidth transmission line devices
D. Goren
,
M. Zelikson
,
+13 authors
D. Harame
Proceedings - Design Automation Conference
2003
Corpus ID: 1485135
This paper expands the on-chip interconnect-aware methodology for high-speed analog and mixed signal design, presented in D…
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1994
1994
Pattern matching and refinement hybrid approach to circuit comparison
G. Pelz
,
U. Roettcher
IEEE Trans. Comput. Aided Des. Integr. Circuits…
1994
Corpus ID: 5157567
We present a new approach to circuit comparison which was developed to combine general applicability with most of the advantages…
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1992
1992
Accurate and Efficient Layout Extraction
N. V. D. Meijs
1992
Corpus ID: 62619038
1989
1989
PACE2: an improved parallel VLSI extractor with parameter extraction
K. Belkhale
,
P. Banerjee
IEEE International Conference on Computer-Aided…
1989
Corpus ID: 1540086
An algorithm, PACE2, is described which is targeted to the second phase of extraction, called the parameter extraction phase. The…
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1987
1987
New algorithms for increased efficiency in hierarchical design rule checking
N. Hedenstierna
,
K. Jeppson
Integr.
1987
Corpus ID: 22394329
1983
1983
Hierarchical Circuit Extraction with Detailed Parasitic Capacitance
G. Tarolli
,
William J. Herman
Design Automation Conference, Proceedings
1983
Corpus ID: 9836813
This paper describes a hierarchical MOS layout verification program called IV. IV extracts a circuit netlist from a MOS layout…
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