Formal equivalence checking

Known as: Equivalence checking 
Formal equivalence checking process is a part of electronic design automation (EDA), commonly used during the development of digital integrated… (More)
Wikipedia

Topic mentions per year

Topic mentions per year

1979-2018
0204019792018

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
Digital applications complexity makes it harder every day to discover and debug behavioral inconsistencies at register transfer… (More)
  • figure I
  • figure 2
  • table 1
  • figure 3
  • table I
Is this relevant?
2013
2013
We present a data driven algorithm for equivalence checking of two loops. The algorithm infers simulation relations using data… (More)
  • figure 1
  • figure 2
  • table 1
  • table 2
  • table 3
Is this relevant?
2010
2010
Formal Equivalence Checking (FEC) is a technique that formally proves the equivalence of a schematics implementation against a… (More)
  • figure 1
  • figure 2
  • figure 3
  • figure 4
  • figure 5
Is this relevant?
2007
2007
Ever-growing complexity is forcing logic design to move above the register transfer level (RTL). For example, functional… (More)
  • figure 2.1
  • figure 2.2
  • figure 2.6
  • figure 2.7
  • figure 2.8
Is this relevant?
Review
2005
Review
2005
A rigorous system-level model (SLM) for a hardware design project is extremely important, often critical. Such a functional model… (More)
  • figure 1
Is this relevant?
Highly Cited
2002
Highly Cited
2002
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient… (More)
  • figure 3
  • figure 4
  • figure 5
  • figure 7
  • figure 6
Is this relevant?
2001
2001
A new approach to sequential verification of designs at different levels of abstraction by symbolic simulation is proposed. The… (More)
  • figure 2.1
  • figure 2.2
  • figure 2.3
  • figure 2.4
  • figure 2.7
Is this relevant?
2001
2001
In this paper, we address on equivalence checking of integer multipliers, especially for the multipliers without structure… (More)
  • figure 1
  • figure 2
  • figure 3
  • figure 7
  • figure 6
Is this relevant?
Highly Cited
2000
Highly Cited
2000
Checking the functional equivalence of sequential circuits is an important practical problem. Because general algorithms for… (More)
  • figure 1
  • figure 2
  • figure 3
  • figure 4
  • figure 5
Is this relevant?
Highly Cited
1997
Highly Cited
1997
This paper presents a verification technique which isspecifically targeted to formally comparing large combinational circuits… (More)
  • figure 2
  • figure 5
  • table 1
Is this relevant?