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Formal equivalence checking

Known as: Equivalence checking 
Formal equivalence checking process is a part of electronic design automation (EDA), commonly used during the development of digital integrated… 
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Related topics

Related topics

22 relations
And-inverter graphBinary decision diagramBoolean satisfiability problemCircuit extraction

Broader (1)

Formal methods

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Property directed reachability with word-level abstraction
SAT-based Property Directed Reachability (PDR) has become the key algorithmic development for unbounded model checking of gate… 
2013
2013
The Value-Passing Calculus
  • Yuxi Fu
  • Theories of Programming and Formal Methods
  • 2013
  • Corpus ID: 5992525
A value-passing calculus is a process calculus in which the contents of communications are values chosen from some data domain… 
2009
2009
Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules
Dynamically reconfigurable hardware combines hardware performance with software-like flexibility and finds increasing use in… 
2007
2007
Random Test Data Generation for Java Classes Annotated with JML Specifications
The hidden states of objects create a barrier to designing and generating test data automatically. For example, the state of an… 
2002
2002
Self-referential verification for gate-level implementations of arithmetic circuits
Verification of gate-level implementations of arithmetic circuits is challenging for a number of reasons: the existence of some… 
2000
2000
AQUILA: An Equivalence Checking System for Large Sequential Designs
In this paper, we present a practical method for verifying the functional equivalence of two synchronous sequential designs. This… 
Highly Cited
2000
Highly Cited
2000
Testing, verification, and diagnosis in the presence of unknowns
Improvement of the accuracy of error and fault diagnosis as well as ATPG for IP-based designs are important problems in industry… 
2000
2000
SpecC System-Level Design Methodology Applied to the Design of a GSM Vocoder
| In this paper we describe the steps and transformations of the SpecC system-level design methodology applied to the example of… 
1999
1999
Algorithms for Satisfiability in Combinational Circuits Based on Backtrack Search and Recursive Learning
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation (EDA). It finds application in test pattern… 
1988
1988
Verification algorithms for VLSI synthesis
A description is given of a theory for, and the application of, a general algorithm for determining whether a given multilevel… 
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