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Formal equivalence checking
Known as:
Equivalence checking
Formal equivalence checking process is a part of electronic design automation (EDA), commonly used during the development of digital integrated…
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Related topics
Related topics
22 relations
And-inverter graph
Binary decision diagram
Boolean satisfiability problem
Circuit extraction
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Broader (1)
Formal methods
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2010
2010
Combinational techniques for sequential equivalence checking
H. Savoj
,
David Berthelot
,
A. Mishchenko
,
R. Brayton
Formal Methods in Computer-Aided Design
2010
Corpus ID: 13349623
Often sequential logic synthesis can lead to substantially easier verification problems, compared to the general-case for…
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Review
2009
Review
2009
Power Reduction Techniques and Flows at RTL and System Level
Anmol Mathur
,
Qi Wang
International Conference on VLSI Design
2009
Corpus ID: 38612621
Power reduction is becoming a critical design criterion for ASIC/SOC designers. Reducing both dynamic and leakage power is…
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2005
2005
Sequential equivalence checking based on k-th invariants and circuit SAT solving
Feng Lu
,
K. Cheng
Tenth IEEE International High-Level Design…
2005
Corpus ID: 15468063
In this paper, we first present the concept of the k-th invariant. In contrast to the traditional invariants that hold for all…
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2004
2004
Structural FSM traversal
D. Stoffel
,
Markus Wedler
,
P. Warkentin
,
W. Kunz
IEEE Transactions on Computer-Aided Design of…
2004
Corpus ID: 13927482
This paper discusses a "structural" technique for traversing the state space of a finite state machine (FSM) and its application…
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2002
2002
Self-referential verification for gate-level implementations of arithmetic circuits
Ying-Tsai Chang
,
K. Cheng
IEEE Transactions on Computer-Aided Design of…
2002
Corpus ID: 10644078
Verification of gate-level implementations of arithmetic circuits is challenging for a number of reasons: the existence of some…
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2001
2001
Induction-based gate-level verification of multipliers
Ying-Tsai Chang
,
K. Cheng
IEEE/ACM International Conference on Computer…
2001
Corpus ID: 11693258
We propose a method based on unrolling the inductive definition of binary number multiplication to verify gate-level…
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2000
2000
AQUILA: An Equivalence Checking System for Large Sequential Designs
Shi-Yu Huang
,
K. Cheng
,
Kuang-Chien Chen
,
C. Huang
,
F. Brewer
IEEE Trans. Computers
2000
Corpus ID: 9625807
In this paper, we present a practical method for verifying the functional equivalence of two synchronous sequential designs. This…
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Highly Cited
2000
Highly Cited
2000
Testing, verification, and diagnosis in the presence of unknowns
Ankur Jain
,
V. Boppana
,
R. Mukherjee
,
J. Jain
,
M. Fujita
,
M. Hsiao
Proceedings of the ... IEEE VLSI Test Symposium
2000
Corpus ID: 32565781
Improvement of the accuracy of error and fault diagnosis as well as ATPG for IP-based designs are important problems in industry…
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1996
1996
XVERSA: An Integrated Graphical and Textual Toolset for the Specification and Analysis of Resource-Bound Real-Time Systems
D. Clarke
,
H. Ben-Abdallah
,
Insup Lee
,
Hong-liang Xie
,
O. Sokolsky
International Conference on Computer Aided…
1996
Corpus ID: 40943830
We present XVERSA, a set of tools for the specification and analysis of resource-bound real-time systems. XVERSA facilitates the…
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1990
1990
Tools for Testing Object-oriented Programs 1
P. Frankl
,
Roong-Ko Doong
1990
Corpus ID: 14362723