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ABC: An Academic Industrial-Strength Verification Tool
TLDR
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs ABC combines scalable logic transformations based on And-Inverter Graphs with a variety of innovative algorithms. Expand
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Efficient implementation of property directed reachability
TLDR
We present the first truly new bit-level symbolic model checking algorithm since Ken McMillan's interpolation based model checking procedure introduced in 2003. Expand
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DAG-aware AIG rewriting: a fresh look at combinational logic synthesis
TLDR
This paper presents a technique for preprocessing combinational logic before technology mapping that scales to very large designs and is several orders of magnitude faster than SIS and MVSIS while offering comparable quality when measured by the quality of the network after mapping. Expand
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Fast Heuristic Minimization of Exclusive-Sums-of-Products
Exclusive-Sums-Of-Products (ESOPs) play an important role in logic synthesis and design-for-test. This paper presents an improved version of the heuristic ESOP minimization procedure proposed inExpand
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Logic Synthesis of Reversible Wave Cascades
TLDR
This paper introduces an algorithm to generate the cascade of reversible complex Maitra terms (called here reversible wave cascade) implementing incompletely specified Boolean functions. Expand
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FRAIGs: A Unifying Representation for Logic Synthesis and Verification
AND-INV graphs (AIGs) are Boolean networks composed of twoinput AND-gates and inverters. In the known applications, such as equivalence checking and technology mapping, AIGs are used to represent andExpand
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An algorithm for bi-decomposition of logic functions
TLDR
We propose a new BDD-based method for decomposition of multi-output incompletely specified logic functions into netlists of two-input logic gates. Expand
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Regularity and Symmetry as a Base for Efficient Realization of Reversible Logic Circuits
We introduce a Reversible Programmable Gate Array (RPGA) based on regular structure to realize binary functions in reversible logic. This structure, called a 2 * 2 Net Structure, allows for moreExpand
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Improvements to Technology Mapping for LUT-Based FPGAs
TLDR
This paper presents several orthogonal improvements to the state-of-the-art lookup table (LUT)-based field-programmable gate array (FPGA) technology mapping. Expand
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Combinational and sequential mapping with priority cuts
TLDR
An algorithm for technology mapping of combinational and sequential logic networks is proposed and applied to mapping into K-input lookup-tables (K-LUTs). Expand
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