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Binary decision diagram
Known as:
Binary Decision Diagrams
, Branching program
, Branching programs
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In computer science, a binary decision diagram (BDD) or branching program is a data structure that is used to represent a Boolean function. On a more…
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Related topics
Related topics
47 relations
And-inverter graph
Automated theorem proving
Binary moment diagram
Boolean satisfiability problem
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Broader (2)
Boolean algebra
Model checking
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2001
2001
Ordered binary decision diagrams
R. Bryant
,
C. Meinel
2001
Corpus ID: 60954039
Ordered Binary Decision Diagrams (OBDDs) play a key role in the automated synthesis and formal verification of digital systems…
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1998
1998
BINARY DECISION DIAGRAM REPRESENTATIONS OF FIREWALL AND ROUTER ACCESS LISTS
S. Hazelhurst
,
Anton Fatti
,
Andrew M. Henwood
1998
Corpus ID: 6035860
Abstract Network firewalls and routers can use a rule database to decide which packets wi ll be allowedfrom one network onto…
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1996
1996
Quantitative fault tree analysis using Binary Decision Diagrams
Roslyn M. Sinnamon
,
J. Andrews
1996
Corpus ID: 62285134
This is a journal article. It was published in RAIRO. Automatique-productique informatique industrielle, 30(8), 1996, pp 1051…
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1996
1996
MORE: an alternative implementation of BDD packages by multi-operand synthesis
A. Hett
,
B. Becker
,
R. Drechsler
Proceedings EURO-DAC '96. European Design…
1996
Corpus ID: 8309772
In this paper we present a new approach for the realization of a BDD package. This approach does not depend on recursive…
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Highly Cited
1995
Highly Cited
1995
Advanced Verification Techniques Based on Learning
J. Jain
,
R. Mukherjee
,
M. Fujita
Design Automation Conference
1995
Corpus ID: 11612769
Design verification poses a very practical problem during circuit synthesis. Learning based verification techniques prove to be…
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Highly Cited
1995
Highly Cited
1995
Test Generation for Path Delay Faults Using Binary Decision Diagrams
D. Bhattacharya
,
P. Agrawal
,
V. Agrawal
IEEE Trans. Computers
1995
Corpus ID: 43640845
A new test generation technique for path delay faults in circuits employing scan/hold type flip-flops is presented. Reduced…
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Highly Cited
1995
Highly Cited
1995
Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment
S. Reddy
,
W. Kunz
,
D. Pradhan
Design Automation Conference
1995
Corpus ID: 11216007
This paper presents a new methodology for formal logic verification for combinational circuits. Specifically, a structural…
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Highly Cited
1992
Highly Cited
1992
Exact calculation of synchronization sequences based on binary decision diagrams
C. Pixley
,
Seh-Woong Jeong
,
G. Hachtel
[] Proceedings 29th ACM/IEEE Design Automation…
1992
Corpus ID: 10004445
A synchronization sequence for a synchronous design D is a sequence of primary input vectors which when applied to any initial…
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1992
1992
Variable ordering for binary decision diagrams
S.-W. Jeong
,
B. Plessier
,
G. Hachtel
,
F. Somenzi
[] Proceedings The European Conference on Design…
1992
Corpus ID: 58363920
Considers the problem of variable ordering in binary decision diagrams (BDD's). The authors present several heuristics for…
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Highly Cited
1990
Highly Cited
1990
A parallel algorithm for constructing binary decision diagrams
S. Kimura
,
E. Clarke
Proceedings., IEEE International Conference on…
1990
Corpus ID: 27466873
A parallel algorithm for constructing binary decision diagrams is described. The algorithms treats binary decision graphs as…
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