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Binary moment diagram
Known as:
Binary Moment Diagrams
A binary moment diagram (BMD) is a generalization of the binary decision diagram (BDD) to linear functions over domains such as booleans (like BDDs…
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2 relations
Binary decision diagram
Broader (1)
Formal methods
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2007
2007
Remarks on Applications of Arithmetic Expressions for Efficient Implementation of Elementary Functions
R. Stankovic
,
J. Astola
2007
Corpus ID: 15371664
It has been recently shown in (1), that elementary mathematical functions (as trigonometric, logarithmic, square root, gaussian…
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2007
2007
Automatic Verification of Arithmetic Circuits using Step-wise Refinement of Term Rewriting Systems
Shobha Vasudevan
,
V. Viswanath
,
R. Sumners
,
J. Abraham
2007
Corpus ID: 18753897
This paper presents a novel technique for proving the correc tness of arithmetic circuit designs described at the Register…
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2006
2006
Representations of Elementary Functions Using Binary Moment Diagrams
Tsutomu Sasao
,
Shinobu Nagayama
IEEE International Symposium on Multiple-Valued…
2006
Corpus ID: 11622605
This paper considers representations for elementary functions such as polynomial, trigonometric, logarithmic, square root, and…
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Review
2004
Review
2004
Equivalence Checking of Arithmetic Circuits
D. Stoffel
,
Evgeny Karibaev
,
I. Kufareva
,
W. Kunz
2004
Corpus ID: 117731529
Although equivalence checking technology has matured greatly during the last few years and designs with millions of gates can be…
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2001
2001
Formal verification of the Pentium(R) 4 multiplier
Roope Kaivola
,
N. Narasimhan
Sixth IEEE International High-Level Design…
2001
Corpus ID: 46329169
We present the formal verification of the floating-point multiplier in the Intel IA-32 Pentium(R)4 microprocessor. The…
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2000
2000
Prove that a faulty multiplier is faulty!?
S. Wefel
,
P. Molitor
ACM Great Lakes Symposium on VLSI
2000
Corpus ID: 14326256
Formal verification of integer multipliers was an open problem for a long time as the size of any reduced ordered binary decision…
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1999
1999
An Exponential Lower Bound on the Size of a Binary Moment Diagram Representing Integer Division (Special Section on Discrete Mathematics and Its Applications)
M. Nakanishi
,
K. Hamaguchi
,
T. Kashiwabara
1999
Corpus ID: 14289344
A binary moment diagram, which was proposed for arithmetic circuit verification, is a directed acyclic graph representing a…
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1998
1998
Arithmetic circuit verification based on word-level decision diagrams
Yirng-An Chen
,
R. Bryant
1998
Corpus ID: 12924781
The division bug in Intel's Pentium processor has demonstrated the importance and the difficulty of verifying arithmetic circuits…
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1996
1996
Modular Verification of Multipliers
Kavita Ravi
,
Abelardo Pardo
,
G. Hachtel
,
F. Somenzi
Formal Methods in Computer-Aided Design
1996
Corpus ID: 984007
We present a new method for the efficient verification of multipliers and other arithmetic circuits. It is based on modular…
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1994
1994
Veri cation of Arithmetic Functionswith Binary Moment
DiagramsRandal
,
E. Bryant
1994
Corpus ID: 14225557
Binary Moment Diagrams (BMDs) provide a canonical representations for linear functions similar to the way Binary Decision…
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