• Publications
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Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization
  • W. Kunz, D. Pradhan
  • Computer Science
  • The IEEE International Symposium on Circuits and…
  • 1 September 1994
Motivated by the problem of test pattern generation in digital circuits, this paper presents a novel technique called recursive learning that is able to perform a logic analysis on digital circuits.Expand
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HANNIBAL: An efficient tool for logic verification based on recursive learning
  • W. Kunz
  • Computer Science
  • Proceedings of International Conference on…
  • 7 November 1993
This paper introduces a new approach to logic verification of combinational circuits, which is based on recursive learning. In particular, the described method efficiently extracts equivalenciesExpand
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Reasoning in Boolean Networks - Logic Synthesis and Verification Using Testing Techniques
Foreword. Preface. 1. Preliminaries. 2. Combinational ATPG. 3. Recursive Learning. 3. And/Or Reasoning Graphs. 5. Logic Optimization. 6. Logic Verification. 7. Conclusions and Future Work.Expand
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Recursive Learning: An attractive alternative to the decision tree for test generation in digital ci
  • W. Kunz, D. Pradhan
  • Computer Science
  • Proceedings International Test Conference
  • 20 September 1992
Most test generators for combinational and sequential circuits use a branch and bound technique in order to systematically explore the search space when trying to generate a test vector. This paperExpand
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AND/OR reasoning graphs for determining prime implicants in multi-level combinational networks
This paper presents a technique to determine prime implicants in multi-level combinational networks. The method is based on a graph representation of Boolean functions called AND/OR reasoning graphs.Expand
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An Algebraic Approach for Proving Data Correctness in Arithmetic Data Paths
This paper proposes a new approach for proving arithmetic correctness of data paths in System-on-Chip modules. It complements existing techniques which are, for reasons of complexity, restricted toExpand
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Logic optimization and equivalence checking by implication analysis
This paper proposes a new approach to multilevel logic optimization based on automatic test pattern generation (ATPG). It shows that an ordinary test generator for single stuck-at faults can be usedExpand
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STABLE: A new QF-BV SMT solver for hard verification problems combining Boolean reasoning with computer algebra
This paper presents a new SMT solver, STABLE, for formulas of the quantifier-free logic over fixed-sized bit vectors (QF-BV). The heart of STABLE is a computer-algebra-based engine which providesExpand
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Verification of integer multipliers on the arithmetic bit level
  • D. Stoffel, W. Kunz
  • Computer Science
  • IEEE/ACM International Conference on Computer…
  • 4 November 2001
One of the most severe shortcomings of currently available equivalence checkers is their inability to verify integer multipliers. In this paper, we present a bit level reverse-engineering techniqueExpand
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Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment
This paper presents a new methodology for formal logic verification for combinational circuits. Specifically, a structural approach is used, based on indirect implications derived by using RecursiveExpand
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