Tsutomu Sasao

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A logic function f has a disjoint bi-decomposition i f can be represented as f = h(g1(X1); g2(X2)), where X1 and X2 are disjoint set of variables, and h is an arbitrary two-variable logic fuction. f has a non-disjoint bidecomposition i f can be represented as f(X1;X2; x) = h(g1(X1; x); g2(X2; x)), where x is the common variable. In this paper, we show a(More)
This paper presents an efficient technique for solving a Boolean matching problem in cell-library binding, where the number of cells in the library is large. As a basis of the Boolean matching, we use the notion NP-representative (NPR); two functions have the same NPR if one can be obtained from the other by a permutation and/or complementation(s) of the(More)
A realization of multiple-output logic functions using a RAM and a sequencer is presented. First, a multiple-output function is represented by an encoded characteristic function for non-zeros (ECFN). Then, it is represented by a cascade of look-up tables (LUTs). And finally, the cascade is simulated by a RAM and a sequencer. Multiple-output functions for(More)
This paper shows a method to represent a multipleoutput function: Encoded characteristic function for nonzero outputs (ECFN). The ECFN uses (n+ u) binary variables to represent an n-input m-output function, where u = dlog2 me. The size of the sum-of-products expressions (SOPs) depends on the encoding method of the outputs. For some class of functions, the(More)
This paper presents a design method of AND-OREXOR three-level networks, where single two-input EXOR gate is used for each output. The network realizes an EXOR of two sum-of-products expressions (EX-SOP): F1 F2, where F1 and F2 are sum-ofproducts expressions (SOPs). The problem is to minimize the total number of di erent products in F1 and F2. A heuristic(More)
This paper proposes an architecture and a synthesis method for high-speed computation of fixed-point numerical functions such as trigonometric, logarithmic, sigmoidal, square root, and combinations of these functions. Our architecture is based on the lookup table (LUT) cascade, which results in a significant reduction in circuit complexity compared to(More)
This paper presents a design method of easily testable AND-EXOR networks. It is an improvement of Reddy and SalujaReddy’s methods, and has the following features: 1) The network uses generalized Reed-Muller expressions (GRMs) instead of Positive Polarity Reed-Muller expressions (PPRMs). The average number of products for GRMs is less than half of that for(More)
This paper surveys seven types of TDDs: General TDD, SOP TDD, ESOP TDD, AND TDD, prime TDD, EXOR TDD, and Kleene TDD. We give new de nitions for SOP TDDs and ESOP TDDs and introduce unifying terminology. After showing some theorems on complexities, we compare the sizes of these TDDs using benchmark functions. Finally, we review important works on TDDs.