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Algorithm-Based Fault Tolerance for Matrix Operations
The rapid progress in VLSI technology has reduced the cost of hardware, allowing multiple copies of low-cost processors to provide a large amount of computational capability for a small cost. InExpand
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  • Open Access
Addressing failures in exascale computing
We present here a report produced by a workshop on ‘Addressing failures in exascale computing’ held in Park City, Utah, 4–11 August 2012. The charter of this workshop was to establish a commonExpand
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  • Open Access
FERRARI: A Flexible Software-Based Fault and Error Injection System
A major step toward the development of fault-tolerant computer systems is the validation of the dependability properties of these systems. Fault/error injection has been recognized as a powerfulExpand
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Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection
This paper evaluates the concurrent error detection capabilities of system-level checks, using fault and error injection. The checks comprise application and system level mechanisms to detect controlExpand
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Test Generation for Microprocessors
The goal of this paper is to develop test generation procedures for testing microprocessors in a user environment. Classical fault detection methods based on the gate and flip-flop level or on theExpand
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Efficient Algorithms for Testing Semiconductor Random-Access Memories
A fault model which views faults in semiconductor random-access memories at a functional level instead of at a basic gate level is presented. An efficient 0(n) algorithm to detect all faults in theExpand
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CRIS: a test cultivation program for sequential VLSI circuits
This paper discusses a novel approach to cultivating a test for combinational and sequential VLSI circuits described hierarchically at the transistor, gate, and higher levels. The approach is basedExpand
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Quantitative evaluation of soft error injection techniques for robust system design
Choosing the correct error injection technique is of primary importance in simulation-based design and evaluation of robust systems that are resilient to soft errors. Many low-level (e.g.,Expand
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  • Open Access
Fault-Tolerant FFT Networks
Two concurrent error detection (CED) schemes are proposed for N-point fast Fourier transform (FFT) networks that consists of log/sub 2/N stages with N/2 two-point butterfly modules for each stage.Expand
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ACCE: Automatic correction of control-flow errors
Detection of control-flow errors at the software level has been studied extensively in the literature. However, there has not been any published work that attempts to correct these errors. Low-costExpand
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  • Open Access