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Prognostics of power MOSFET
This paper demonstrates how to apply prognostics to power MOSFETs (metal oxide field effect transistor). The methodology uses thermal cycling to age devices and Gaussian process regression to perform
Accelerated aging system for prognostics of power semiconductor devices
Prognostics is an engineering discipline that focuses on estimation of the health state of a component and the prediction of its remaining useful life (RUL) before failure. Health state estimation is
ESD Design for Analog Circuits
TLDR
Standard and ESD Devices in Integrated Process Technologies and System-Level and Discrete Components ESD.
High holding voltage cascoded LVTSCR structures for 5.5-V tolerant ESD protection clamps
This paper presents a new design concept for the control of the holding voltage of LVTSCR ESD protection structures by realizing a negative feedback in the p emitter. The negative feedback is
Physical Limitations of Semiconductor Devices
This book provides an important link between the theoretical knowledge in the field of non-linier physics and practical application problems in microelectronics. It delivers different levels of
Improving the ESD self-protection capability of integrated power NLDMOS arrays
The self-protection capability (SPC) of integrated power arrays in ESD regimes has been studied for the case of integrated 100 V NLDMOS arrays in a BCD process. A new practical methodology for array
Turn-off characteristics of the CMOS snapback ESD protection devices - new insights and its implications
The residual voltage across the ESD snapback protection device after its turn-off is one of the key parameters that must be considered for efficient ESD protection design. Turn-off characteristics of
RF ESD protection strategies - the design and performance trade-off challenges
TLDR
The conventional approach using diodes with power clamp is compared with novel approaches such as plug-and-play passive elements and full or partial circuit-ESD co-design.
A dual-base triggered SCR with very low leakage current and adjustable trigger voltage
A new dual-base triggered SCR is presented. By adjusting the device sizings in the trigger circuit, the designer sets the trigger voltage to an application appropriate-value. The turn on time is
SCCF — System to component level correlation factor
As a first step towards correlation of system level ESD robustness based on component level ESD results, on-wafer Human Metal Model (HMM) measurements are compared with on-wafer HBM for a wide range
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