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Source-synchronous

Known as: Source synchronous, Source syncronous 
Source-Synchronous clocking refers to a technique used for timing symbols on a digital interface. Specifically, it refers to the technique of having… Expand
Wikipedia

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
A cognitive tri-band transmitter (TX) with a forwarded clock using multiband signaling and high-order digital signal modulations… Expand
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2016
2016
Single-mode wavelength-division multiplexing (WDM) optical links are an attractive technology to meet the growing interconnect… Expand
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2012
2012
This paper presents a novel all-digital CDR scheme in 90 nm CMOS. Two independently adjustable clock phases are generated from a… Expand
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2012
2012
While continued scaling of feature sizes allows for an ever increasing number of cores in modern MPSoCs, power reduction and… Expand
Highly Cited
2009
Highly Cited
2009
A high-speed inductive-coupling link is presented. It communicates at a data rate of 11 Gb/s for a communication distance of 15… Expand
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2009
2009
  • Zhiyi Yu, B. Baas
  • IEEE Transactions on Very Large Scale Integration…
  • 2009
  • Corpus ID: 15916501
Chip multiprocessors with globally asynchronous locally synchronous (GALS) clocking styles are promising candidates for… Expand
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2009
2009
This paper presents the design of a 64-PE folded-torus intra-chip communication fabric used to provide guaranteed throughput in… Expand
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2006
2006
This article presents a modular approach for testing multigigahertz, multilane digital devices with source-synchronous I/O buses… Expand
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2005
2005
Increasing complexity of a system-on-chip design demands efficient on-chip interconnection architecture such as on-chip network… Expand
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2005
2005
A structured packet-switched networks-on-chip (NoC) is designed and implemented for high-performance heterogeneous SoC design… Expand
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