Source-synchronous

Known as: Source synchronous, Source syncronous 
Source-Synchronous clocking refers to a technique used for timing symbols on a digital interface. Specifically, it refers to the technique of having… (More)
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Topic mentions per year

Topic mentions per year

1999-2018
051019992018

Papers overview

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2014
2014
Energy-efficient networks-on-chip (NoCs) are key enablers for exa-scale computation by shifting power budget from communication… (More)
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2011
2011
High-speed links which employ source synchronous clocking architectures have the ability to track correlated jitter between clock… (More)
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2011
2011
Source synchronous links for use in multi-synchronous networks-on-chip (NoCs) are becoming the most vulnerable points for correct… (More)
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2009
2009
In this paper, a variation-tolerant low-power source-synchronous multicycle bus (SSMCB) interconnect scheme is proposed. This… (More)
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2006
2006
This article presents a modular approach for testing multigigahertz, multilane digital devices with source-synchronous I/O buses… (More)
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2005
2005
Source-synchronous double-data-rate (DDR) signaling is widely used in electrical interconnects to eliminate clock recovery and to… (More)
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2004
2004
Jitter significantly limits the maximum achievable data rates (MADR) over high-speed source-synchronous I/O links. In this paper… (More)
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2003
2003
Jitter significantly limits the maximum achievable data rates (MADR) over high-speed source-synchronous I/O links. In this paper… (More)
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2002
2002
Source synchronous simultaneous bi-directional (SS-SBD) link modeling and correlation to measured data are discussed. Source… (More)
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2002
2002
System designers are faced with the challenge of increasing inter-chip bandwidth without adding IO cells to an ASIC library. One… (More)
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