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Source-synchronous

Known as: Source synchronous, Source syncronous 
Source-Synchronous clocking refers to a technique used for timing symbols on a digital interface. Specifically, it refers to the technique of having… Expand
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Papers overview

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2012
2012
While continued scaling of feature sizes allows for an ever increasing number of cores in modern MPSoCs, power reduction and… Expand
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2012
2012
A source synchronous I/O system based on high-density silicon carrier interconnects is introduced. Benefiting from the advantages… Expand
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2011
2011
Communication costs, which have the potential to throttle design performance as scaling continues, are mathematically modeled and… Expand
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2010
2010
This paper presents a globally-asynchronous locally-synchronous (GALS)-compatible circuit-switched on-chip network that is well… Expand
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2009
2009
Wave pipelining has gained attention for NoC interconnect by its promise of high bandwidth using simple circuits. Reliability… Expand
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2008
2008
This paper describes the design and implementation of a 8times5 Gb/s source-synchronous receiver in a 0.13 mum CMOS technology… Expand
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2006
2006
This article presents a modular approach for testing multigigahertz, multilane digital devices with source-synchronous I/O buses… Expand
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Highly Cited
2005
Highly Cited
2005
A source-synchronous I/O link with adaptive receiver-side equalization has been implemented in 0.13-/spl mu/m bulk CMOS… Expand
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2004
2004
A majority of digital logic devices receives stimulus from an external system clock and sends information out on bus pins which… Expand
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2002
2002
We present a novel implementation of source synchronous communication for communication between clock domains within a SOC. Our… Expand
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