Skip to search form
Skip to main content
Skip to account menu
Semantic Scholar
Semantic Scholar's Logo
Search 237,332,196 papers from all fields of science
Search
Sign In
Create Free Account
Source-synchronous
Known as:
Source synchronous
, Source syncronous
Source-Synchronous clocking refers to a technique used for timing symbols on a digital interface. Specifically, it refers to the technique of having…
Expand
Wikipedia
(opens in a new tab)
Create Alert
Alert
Related topics
Related topics
10 relations
Clock recovery
HyperTransport
Itanium
Media-independent interface
Expand
Broader (1)
Clock signal
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
Design and Implementation of an On-chip Multistage Network Topology for System On-Chip
S. Sunkara
2014
Corpus ID: 212600829
— This paper presents the silicon-proven design of a novel on-chip network to support guaranteed traffic permutation in…
Expand
2012
2012
On-chip source synchronous interface timing test scheme with calibration
H. Kim
,
J. Abraham
Design, Automation and Test in Europe
2012
Corpus ID: 1102408
This paper presents an on-chip test circuit with a high resolution for testing source synchronous interface timing. Instead of a…
Expand
2011
2011
A Four-Stage Mesochronous Synchronizer with BackPressure and Buffering for Short and Long Range Communications
Dmitry Verbitsky
,
R. Ginosar
2011
Corpus ID: 17142937
A four-stage mesochronous synchronizer is described. It enables low latency and full throughput crossing of boundaries of same…
Expand
2011
2011
Advanced calibration techniques for high-speed source-synchronous interfaces
F. Plessas
,
A. Alexandropoulos
,
Sotiris Koutsomitsos
,
E. Davrazos
,
M. Birbas
IET Computers & Digital Techniques
2011
Corpus ID: 18997723
Advanced and dynamic calibration techniques for maximising the link performance of parallel source-synchronous interfaces are…
Expand
2011
2011
Reconfigurable interconnect infrastructure for multi-FPGA-based adaptive multiprocessing systems
Faizal Arya Samman
,
F. Philipp
,
M. Glesner
1st International Workshop on Computing in…
2011
Corpus ID: 10085818
A concept for reconfigurable communication infrastructure for networked control systems is presented in this paper. The…
Expand
Review
2009
Review
2009
Welcome to the 2009 Symposium on VLSI Circuits
M. Mizuno
,
A. Amerasekera
2009
Corpus ID: 110488960
You are cordially invited to attend the 2009 Symposium on VLSI Circuits, to be held on June 16-18th, 2009, at the Rihga Royal…
Expand
2008
2008
PORTABLE CLOCK RECOVERY CIRCUITS ( CRCS ) FOR ON-CHIP AND OFF-CHIP SERIAL DATA COMMUNICATION
M. Elrabaa
2008
Corpus ID: 14912362
High data rates and reliability have made serial communications the most preferred inter-chip communication method. Applications…
Expand
2006
2006
Syncronous colorectal carcinoma.
G. Modica
,
M. Cajozzo
,
+8 authors
G. Modica
2006
Corpus ID: 79573969
2002
2002
White Paper The Need for Dynamic Phase Alignment in High-Speed FPGAs
2002
Corpus ID: 54172152
With the explosion of data, voice, and video traffic across many markets, FPGAs are now being used in applications that require…
Expand
1999
1999
DDR-SDRAM, HIGH-SPEED, SOURCE-SYNCHRONOUS INTERFACES CREATE DESIGN CHALLENGES
H. A. Collins
,
R. Nikel
1999
Corpus ID: 43991447
With source-synchronous interfaces, data and clock transport from a transmitter to a receiver, and the receiver interface uses…
Expand