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Itanium
Known as:
Iantium
, Itanium microprocessor
, Itanium (original)
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(For more details on the technical architecture, not chip implementations, see IA-64.) Itanium (/aɪˈteɪniəm/ eye-TAY-nee-əm) is a family of 64-bit…
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Anaconda
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Clemens C. J. Roothaan
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2012
2012
En mouvement, du modèle à la puce : Pour des systèmes de vision polyvalents et performants
Antoine Manzanera
2012
Corpus ID: 32518456
Meme s'il n'existe toujours pas de systeme visuel artificiel dont les performances soient comparables a notre vision biologique…
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2008
2008
Simulation of the Lattice QCD and Technological Trends in Computation
K. Ibrahim
,
J. Jaeger
,
+9 authors
P. Roudeau
2008
Corpus ID: 15709623
Simulation of Lattice QCD is a challenging computational problem. Currently, technological trends in computation show multiple…
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2008
2008
Assembly Code Analysis Using Stochastic Process Algebra
L. Djoudi
,
L. Kloul
European Performance Engineering Workshop
2008
Corpus ID: 17481722
Currently compilers contain a large number of optimisations which are based on a set of heuristics that are not guaranteed to be…
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2007
2007
On Composing Matrix Multiplication from Kernels
Bryan May
2007
Corpus ID: 18932768
Matrix multiplication is often treated as a basic unit of computation in terms of which other operations are implemented…
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2007
2007
An Intelligent Mechanism to Explore a Two-Level Cache Hierarchy Considering Energy Consumption and Time Performance
A. Silva-Filho
,
C.J.A. Filho
,
R. M. Lima
,
D. Falcão
,
F. Cordeiro
,
M. Lima
Symposium on Computer Architecture and High…
2007
Corpus ID: 15225323
Cache memory hierarchy contributes positively to system performance. Moreover, tuning cache architectures in platforms for…
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2005
2005
Enabling technologies for innovative new materials
R. Gomperts
,
E. Renner
,
M. Mehta
2005
Corpus ID: 99182986
12 NOVEMBER 2005 • AMERICAN LABORATORY In the quest to develop innovative products, researchers are increasingly relying on…
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2005
2005
Unpredication, unscheduling, unspeculation: reverse engineering Itanium executables
Noah Snavely
,
S. Debray
,
G. Andrews
IEEE Transactions on Software Engineering
2005
Corpus ID: 2406458
EPIC (explicitly parallel instruction computing) architectures, exemplified by the Intel Itanium, support a number of advanced…
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2005
2005
Scalable Cross-Architecture Predictions of Memory Hierarchy Response for Scientific Applications
Gabriel Marin mgabi
2005
Corpus ID: 14093250
The gap between processor and memory speeds has been growing with each new generation of microprocessors. As a result, memory…
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2003
2003
NUCA : A Non-Uniform Cache Access Architecture for Wire-Delay Dominated On-Chip Caches
Changkyu Kim
,
D. Burger
,
S. Keckler
2003
Corpus ID: 12863113
This paper describes Non-Uniform Cache Access (NUCA) designs, which solve the on-chip wire delay problem for future large…
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2002
2002
Quantitative evaluation of the register stack engine and optimizations for future Itanium processors
R. Weldon
,
Steven S. Chang
,
+4 authors
John Paul Shen
Proceedings Sixth Annual Workshop on Interaction…
2002
Corpus ID: 40482370
This paper examines the efficiency of the register stack engine (RSE) in the canonical Itanium architecture, and introduces novel…
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