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CPU cache
Known as:
Full associative
, Micro-operation cache
, Exclusive cache
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A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data…
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Related topics
Related topics
50 relations
Address space
Advanced Synchronization Facility
AltiVec
Bus snooping
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Broader (1)
Computer memory
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Review
2012
Review
2012
Comprehensive Topological Analysis of Conductive and Inductive Charging Solutions for Plug-In Electric Vehicles
A. Khaligh
,
S. Dusmez
IEEE Transactions on Vehicular Technology
2012
Corpus ID: 206815719
The impending global energy crisis has opened up new opportunities for the automotive industry to meet the ever-increasing demand…
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Highly Cited
2007
Highly Cited
2007
MiniSec: A Secure Sensor Network Communication Architecture
Mark Luk
,
Ghita Mezzour
,
A. Perrig
,
V. Gligor
International Symposium on Information Processing…
2007
Corpus ID: 6758379
Secure sensor network communication protocols need to provide three basic properties: data secrecy, authentication, and replay…
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Highly Cited
2007
Highly Cited
2007
A log buffer-based flash translation layer using fully-associative sector translation
Sang-Won Lee
,
Dong-Joo Park
,
Tae-Sun Chung
,
Dong-Ho Lee
,
Sangwon Park
,
Ha-Joo Song
TECS
2007
Corpus ID: 14494226
Flash memory is being rapidly deployed as data storage for mobile devices such as PDAs, MP3 players, mobile phones, and digital…
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Highly Cited
2005
Highly Cited
2005
Predicting inter-thread cache contention on a chip multi-processor architecture
Dhruba Chandra
,
Fei Guo
,
Seongbeom Kim
,
Yan Solihin
International Symposium on High-Performance…
2005
Corpus ID: 11647307
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a chip multi-processor (CMP…
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Highly Cited
2004
Highly Cited
2004
Fair cache sharing and partitioning in a chip multiprocessor architecture
Seongbeom Kim
,
Dhruba Chandra
,
Yan Solihin
Proceedings. 13th International Conference on…
2004
Corpus ID: 1916109
This paper presents a detailed study of fairness in cache sharing between threads in a chip multiprocessor (CMP) architecture…
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Review
2002
Review
2002
An Overview of Cache Optimization Techniques and Cache-Aware Numerical Algorithms
M. Kowarschik
,
Christian Weiß
Algorithms for Memory Hierarchies
2002
Corpus ID: 7832591
In order to mitigate the impact of the growing gap between CPU speed and main memory performance, today’s computer architectures…
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Highly Cited
2001
Highly Cited
2001
The microarchitecture of the Pentium 4 processor
G. Hinton
,
David J. Sager
,
Mike Upton
2001
Corpus ID: 59765897
This paper describes the Intel ® NetBurst™ microarchitecture of Intel’s new flagship Pentium ® 4 processor. This…
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Highly Cited
2001
Highly Cited
2001
Cacti 3. 0: an integrated cache timing, power, and area model
Premkishore Shivakumar
,
N. Jouppi
2001
Corpus ID: 107950264
tion in 1982. We focus on information technology that is relevant to the technical strategy of the Corporation, and that has the…
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Highly Cited
1998
Highly Cited
1998
Water flow through temperate glaciers
A. Fountain
,
J. Walder
1998
Corpus ID: 21714814
Understanding water movement through a glacier is fundamental to several critical issues in glaciology, including glacier…
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Highly Cited
1997
Highly Cited
1997
The performance of μ-kernel-based systems
Hermann Härtig
,
M. Hohmuth
,
J. Liedtke
,
S. Schönberg
,
J. Wolter
Symposium on Operating Systems Principles
1997
Corpus ID: 1706253
First-generation μ-kernels have a reputation for being too slow and lacking sufficient flexibility. To determine whether L4, a…
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