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Parallel Metropolis coupled Markov chain Monte Carlo for Bayesian phylogenetic inference
TLDR
We propose Metropolis coupled MCMC [(MC)(3)], a variant of MCMC, allows multiple peaks in the landscape of trees to be more readily explored, but at the cost of increased execution time. Expand
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TreadMarks: Distributed Shared Memory on Standard Workstations and Operating Systems
TLDR
This paper presents a performance evaluation of TreadMarks running on Ultrix using DECstation5000/240's that are connected by a 100-Mbps switch-based ATM LAN and a 10-Mbps Ethernet. Expand
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ThreadMarks: Shared Memory Computing on Networks of Workstations
TLDR
In this paper, we discuss our experience with parallel computing on networks of workstations using the TreadMarks distributed shared memory (DSM) system. Expand
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Peer-to-peer information retrieval using self-organizing semantic overlay networks
TLDR
We present pSearch, a decentralized non-flooding P2P information retrieval system that can achieve performance comparable to centralized information retrieval systems by searching only a small number of nodes. Expand
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Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling
TLDR
We describe an alternative approach, which we call a multiple clock domain (MCD) processor, in which the chip is divided into several clock domains, within which independent voltage and frequency scaling can be performed. Expand
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Characterizing and predicting program behavior and its variability
TLDR
We study the time-varying behavior of programs using metrics derived from hardware counters on two different microarchitectures and show that programs exhibit significant behavior variation even at a granularity of millions of instructions. Expand
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Incremental and interactive sequence mining
TLDR
In this paper, we propose novel techniques for maintaining sequences in the presence of a) database updates, and b) user interaction (e.g. modifying mining parameters). Expand
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Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
TLDR
In this paper, we propose a cache and TLB layout and design that leverages repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. Expand
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Hybrid Global-Local Indexing for Efficient Peer-to-Peer Information Retrieval
Content-based full-text search still remains a particularly challenging problem in peer-to-peer (P2P) systems. Traditionally, there have been two index partitioning structures--partitioning based onExpand
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Reducing the complexity of the register file in dynamic superscalar processors
TLDR
In this paper, we propose a register file organization that reduces register file size and port requirements for a given amount of ILP. Expand
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