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Bus snooping
Known as:
Cache snooping
, Snoop cycle
, Bus sniffing
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Bus snooping or bus sniffing is a scheme that a coherency controller (snooper) in a cache monitors or snoops the bus transactions in order to…
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Related topics
Related topics
16 relations
CPU cache
Cache (computing)
Cache coherence
Cache invalidation
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Protecting User Privacy in a Multi-Path Information-Centric Network Using Multiple Random-Caches
W. Chu
,
Li-Fang Wang
,
Zejun Jiang
,
Chinchen Chang
Journal of Computer Science and Technology
2017
Corpus ID: 10625090
In-network caching is a fundamental mechanism advocated by information-centric networks (ICNs) for efficient content delivery…
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Highly Cited
2015
Highly Cited
2015
Going Wild: Large-Scale Classification of Open DNS Resolvers
Marc Kührer
,
Thomas Hupperich
,
Jonas Bushart
,
C. Rossow
,
Thorsten Holz
Internet Measurement Conference
2015
Corpus ID: 10408484
Since several years, millions of recursive DNS resolvers are-deliberately or not-open to the public. This, however, is counter…
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2013
2013
Building expressive, area-efficient coherence directories
Lei Fang
,
Peng Liu
,
Qi Hu
,
M. Huang
,
G. Jiang
Proceedings of the 22nd International Conference…
2013
Corpus ID: 2957071
Mainstream chip multiprocessors already include a significant number of cores that make straightforward snooping-based cache…
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2012
2012
Detecting router cache snooping in Named Data Networking
N. Ntuli
,
Sunyoung Han
International Conference on ICT Convergence (ICTC…
2012
Corpus ID: 19217251
Named Data Networking (NDN) is an example of studies that attempt to adapt the Internet architecture to new Internet usage…
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Highly Cited
2012
Highly Cited
2012
Vigilare: toward snoop-based kernel integrity monitor
Hyungon Moon
,
Hojoon Lee
,
Jihoon Lee
,
Kihwan Kim
,
Y. Paek
,
Brent Byunghoon Kang
CCS
2012
Corpus ID: 3441982
In this paper, we present Vigilare system, a kernel integrity monitor that is architected to snoop the bus traffic of the host…
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2007
2007
Streaming consistency: a model for efficient MPSoC design
J. V. D. Brand
,
M. Bekooij
10th Euromicro Conference on Digital System…
2007
Corpus ID: 16168602
Multiprocessor systems-on-chip (MPSoC) with distributed shared memory and caches are flexible when it comes to inter-processor…
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2005
2005
A low-power 2.5-GHz 90-nm level 1 cache and memory management unit
J. Haigh
,
M. Wilkerson
,
Jay B. Miller
,
T. Beatty
,
S. Strazdus
,
L. Clark
IEEE Journal of Solid-State Circuits
2005
Corpus ID: 24079055
The design of a 90-nm virtually addressed cache subsystem with separate 32-kB instruction and data caches is described. The…
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2003
2003
A distributed cache architecture for routing in hierarchical QoS-capable networks
M. Rezvan
,
K. Pawlikowski
,
H. Sirisena
IEEE International Conference on Communications…
2003
Corpus ID: 22985940
The route computing overhead caused by on-demand calculation of QoS routes, especially in large networks with heavy traffic, is a…
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1994
1994
PowerPC processors
A. Marsala
,
B. Kanawati
Proceedings of 26th Southeastern Symposium on…
1994
Corpus ID: 57156764
In October of 1991, IBM, Apple, and Motorola formed an alliance to produce a new microprocessor family named the PowerPC. Less…
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Highly Cited
1985
Highly Cited
1985
Implementing a cache consistency protocol
R. Katz
,
S. Eggers
,
D. Wood
,
C. Perkins
,
R. G. Sheldon
ISCA '85
1985
Corpus ID: 15406054
We present an ownership-based multiprocessor cache consistency protocol, designed for implementation by a single chip VLSI cache…
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