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Bus snooping
Known as:
Cache snooping
, Snoop cycle
, Bus sniffing
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Bus snooping or bus sniffing is a scheme that a coherency controller (snooper) in a cache monitors or snoops the bus transactions in order to…
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Related topics
Related topics
16 relations
CPU cache
Cache (computing)
Cache coherence
Cache invalidation
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2008
2008
An analytical study of a new high performance computer architecture
Cheng-Hsien Tung
2008
Corpus ID: 60574450
The need for large scale parallel computer systems has been intensified by the number of applications which require manipulation…
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2007
2007
Implementation of coarse-grain coherence tracking support in ring-based multiprocessors
E. Cote
2007
Corpus ID: 63965019
Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-10-24 10:16:47.81
2002
2002
On the Tamability of the Location Consistency Memory Model
C. Wallace
,
G. Tremblay
,
J. N. Amaral
International Conference on Parallel and…
2002
Corpus ID: 7763723
Gao and Sarkar have proposed Location Consistency (LC), the weakest memory model described in the literature to date for shared…
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2001
2001
Global Bus RFQ ok / error Look-Up / Response Tb REQACK / NAK Ta Storage State & Tag Cache / AM Controller
Sangyeun Cho
,
Jinseok Kong
,
Gyungho Lee
2001
Corpus ID: 17209279
Cache Only Memory Architecture has potential of decreasing global bus traffic in shared bus multiprocessors, reducing the speed…
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2000
2000
A distributed cache architecture for quality-of-service routing in communication networks
M. Rezvan
2000
Corpus ID: 28615775
The rapid advances in telecommunication and Internet technologies is the driving force behind the emergence of a new generation…
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1995
1995
Multiple-bus, scalable, shared-memory multiprocessors
M. Carlton
,
A. Despain
,
R. Katz
1995
Corpus ID: 61681151
This dissertation presents the design and evaluation of a multiple-bus, cache-coherent, scalable, shared-memory, multiprocessor…
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1993
1993
The 1553 Advanced Communication Engine (1553-ACE)
S. Friedman
IEEE Aerospace and Electronic Systems Magazine
1993
Corpus ID: 114944903
The next-generation 1553 terminals will address the concerns of reducing the size, power, and cost and adding features required…
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1990
1990
An on-chip 72 K pseudo two-port cache memory subsystem
C.-M. S. Chuang
,
T. Mukherjee
,
+5 authors
Chekib Akrout
Digest of Technical Papers., Symposium on VLSI…
1990
Corpus ID: 36515517
A CMOS VLSI cache memory subsystem, which includes a 72 K cache memory, a 11 K tag memory, a 1.3 K state array, two special…
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1990
1990
Architecture and design of a pseudo two-port VLSI snoopy cache memory
C.-M. S. Chuang
,
A. Bruss
Annual European Computer Conference
1990
Corpus ID: 54017065
A CMOS VLSI cache memory subsystem that includes a 72 K-bit cache memory, an 11 K-bit tag memory, a 1.3 K-bit state array, two…
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