Skip to search formSkip to main content
You are currently offline. Some features of the site may not work correctly.

Bus snooping

Known as: Cache snooping, Snoop cycle, Bus sniffing 
Bus snooping or bus sniffing is a scheme that a coherency controller (snooper) in a cache monitors or snoops the bus transactions in order to… Expand
Wikipedia

Related topics

Related topics

16 relations
CPU cacheCache (computing)Cache coherenceCache invalidation
Expand

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
Analysing Censorship Circumvention with VPNs Via DNS Cache Snooping
Anecdotal evidence suggests an increasing number of people are turning to VPN services for the properties of privacy, anonymity… Expand
  • figure 1
  • figure 2
  • figure 3
  • figure 4
Highly Cited
2015
Highly Cited
2015
Going Wild: Large-Scale Classification of Open DNS Resolvers
Since several years, millions of recursive DNS resolvers are-deliberately or not-open to the public. This, however, is counter… Expand
  • figure 1
  • table 1
  • table 2
  • table 3
  • table 4
2013
2013
Building expressive, area-efficient coherence directories
Mainstream chip multiprocessors already include a significant number of cores that make straightforward snooping-based cache… Expand
  • figure 1
  • figure 4
  • figure 2
  • figure 5
  • figure 3
Highly Cited
2012
Highly Cited
2012
Vigilare: toward snoop-based kernel integrity monitor
In this paper, we present Vigilare system, a kernel integrity monitor that is architected to snoop the bus traffic of the host… Expand
  • figure 1
  • figure 2
  • figure 3
  • figure 4
  • figure 5
2012
2012
Detecting router cache snooping in Named Data Networking
Named Data Networking (NDN) is an example of studies that attempt to adapt the Internet architecture to new Internet usage… Expand
  • figure 1
  • figure 2
  • figure 4
  • figure 3
2007
2007
Streaming consistency: a model for efficient MPSoC design
Multiprocessor systems-on-chip (MPSoC) with distributed shared memory and caches are flexible when it comes to inter-processor… Expand
  • figure 1
  • figure 3
  • figure 5
  • figure 7
  • figure 6
2007
2007
Streaming memory consistency for efficient MPSoC design
Multiprocessor systems-on-chip (MPSoC) with distributed shared memory and caches are flexible when it comes to inter-processor… Expand
  • figure 1
  • figure 2
  • figure 3
  • figure 4
  • figure 5
2003
2003
A distributed cache architecture for routing in hierarchical QoS-capable networks
The route computing overhead caused by on-demand calculation of QoS routes, especially in large networks with heavy traffic, is a… Expand
  • figure 1
  • figure 2
  • figure 3
  • figure 6
2002
2002
On the Tamability of the Location Consistency Memory Model
Gao and Sarkar have proposed Location Consistency (LC), the weakest memory model described in the literature to date for shared… Expand
  • figure 1
  • figure 2
  • figure 3
Highly Cited
1985
Highly Cited
1985
Implementing a cache consistency protocol
We present an ownership-based multiprocessor cache consistency protocol, designed for implementation by a single chip VLSI cache… Expand
  • figure 2.1
  • figure 3.1
  • figure 3.3
  • figure 3.2
  • figure 3.4
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy, Terms of Service, and Dataset License
ACCEPT & CONTINUE