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HyperTransport
Known as:
HT
, Lightning Data Transport
, Direct Connect Architecture
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HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a technology for interconnection of computer processors. It is a…
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50 relations
32-bit
AGESA
AMD 10h
AMD 580 chipset series
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
Shared hardware accelerator architectures for heterogeneous MPSoCs
Bouthaina Damak
,
M. Baklouti
,
S. Niar
,
M. Abid
Reconfigurable Communication-centric Systems-on…
2013
Corpus ID: 27960639
Heterogeneous Multiprocessor System-on-Chip (Ht-MPSoC) platforms are being increasingly deployed in high performance embedded…
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2013
2013
GaN-Based LEDs With an HT-AlN Nucleation Layer Prepared on Patterned Sapphire Substrate
Chung-Ying Chang
,
S. Chang
,
C. H. Liu
,
Shuguang Li
,
E. Chen
IEEE Photonics Technology Letters
2013
Corpus ID: 26793159
We report the growth and fabrication of GaN-based light-emitting diodes (LEDs) with a high-temperature (HT) AlN nucleation on…
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Review
2009
Review
2009
Quantifying Network Contention on Large Parallel Machines
A. Bhatele
,
L. Kalé
Parallel Processing Letters
2009
Corpus ID: 632832
In the early years of parallel computing research, significant theoretical studies were done on interconnect topologies and…
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2009
2009
High Throughput architecture for OCTAGON Network on Chip
Mohamed A. Abd El-Ghany
,
M. El-Moursy
,
D. Korzec
,
M. Ismail
International Conference on Electronics, Circuits…
2009
Corpus ID: 30058264
High Throughput Octagon architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases…
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2009
2009
Memory Migration on Next-Touch
Brice Goglin
,
N. Furmento
2009
Corpus ID: 17041590
NUMA abilities such as explicit migration of memory buffers enable flexible placement of data buffers at runtime near the tasks…
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Review
2007
Review
2007
First Silicon Functional Validation and Debug of Multicore Microprocessors
T. J. Foster
,
Dennis L. Lastor
,
P. Singh
IEEE Transactions on Very Large Scale Integration…
2007
Corpus ID: 12564090
Microprocessor designs are increasingly moving towards multiple cores on a single die. Validating memory consistency, coherency…
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2007
2007
Secure and Authenticated Communication in Chip-Level Microcomputer Bus Systems with Tree Parity Machines
Sascha Mühlbach
,
S. Wallner
International Conference on Embedded Computer…
2007
Corpus ID: 15159489
The protection of chip-level microcomputer bus systems in embedded devices is essential to prevent the growing number of hardware…
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2006
2006
Simulation and measurement of high speed serial link performance in a dense, thin core flip chip package
M. Rowlands
,
S. Rosser
Electronic Components and Technology Conference
2006
Corpus ID: 38404379
The speed of differential digital signals, such as 12.5 Gb/s, have increased enough to be degraded by semiconductor packaging…
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2005
2005
BladeCenter processor blades, I/O expansion adapters, and units
James E. Hughes
,
Michael L. Scollard
,
+10 authors
Dhruv M. Desai
IBM Journal of Research and Development
2005
Corpus ID: 17591811
This paper describes the electrical architecture and design of the IBM eServerTM BladeCenter® processor blades, expansion blades…
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2005
2005
Challenges in High Speed Interface Testing
S. Abdennadher
,
S. Shaikh
Asian Test Symposium
2005
Corpus ID: 23627463
There is a common trend towards the incorporation of Serial Interfaces into Systems-on-Chips (SoC), both for inter-chip and intra…
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