• Publications
  • Influence
Wideband low-distortion delta-sigma ADC topology
A /spl Delta//spl Sigma/ topology with reduced sensitivity to opamp nonlinearities is described. The technique is effective even for very low oversampling ratios, and can be used for any modulationExpand
  • 551
  • 34
Background calibration techniques for multistage pipelined ADCs with digital redundancy
TLDR
The proposed digital background calibration scheme, applicable to multistage (pipelined or algorithmic/cyclic) analog-to-digital converters (ADCs), corrects the linearity errors resulting from capacitor mismatches and finite opamp gain. Expand
  • 217
  • 27
  • PDF
Merged capacitor switching based SAR ADC with highest switching energy-efficiency
TLDR
A modified merged capacitor switching (MCS) scheme is proposed for the successive approximation register (SAR) analogue-to-digital converter (ADC). Expand
  • 225
  • 24
  • PDF
Digitally synthesized stochastic flash ADC using only standard digital cells
TLDR
An ADC is synthesized entirely from Verilog code in 90nm digital CMOS using a standard digital cell library. Expand
  • 113
  • 14
  • PDF
A Digital PLL With a Stochastic Time-to-Digital Converter
TLDR
A new dual-loop digital phase-locked loop (DPLL) architecture is presented. Expand
  • 117
  • 11
  • PDF
A CMOS self-calibrating frequency synthesizer
TLDR
A programmable phase-locked-loop (PLL)-based frequency synthesizer, capable of automatically adjusting the nominal center frequency of the voltage-controlled oscillator (VCO) to an optimum value is described. Expand
  • 143
  • 10
  • PDF
Ring amplifiers for switched-capacitor circuits
TLDR
To overcome the challenges that CMOS process scaling has imposed on the design of switched-capacitor amplification circuits, designers must consider a growing number of design tradeoffs and employ new circuit techniques in order to achieve required accuracies, often at a cost of added power and complexity. Expand
  • 83
  • 10
Sturdy MASH - modulator
A new Δ-Σ modulator is proposed. Its operation is similar to that of a multi-stage noise-shaping structure but requires no digital noise cancellation filters. Thus, the need for matching requiredExpand
  • 52
  • 10
A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy
TLDR
In this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. Expand
  • 132
  • 9
  • PDF
A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique
TLDR
A time-shifted correlated double sampling (CDS) technique is proposed in the design of a 10-bit 100-MS/s pipelined ADC, allowing the active opamp blocks to be replaced by simple cascoded CMOS inverters. Expand
  • 94
  • 9
...
1
2
3
4
5
...