• Publications
  • Influence
A Digital PLL With a Stochastic Time-to-Digital Converter
TLDR
A new dual-loop digital phase-locked loop (DPLL) architecture is presented. Expand
  • 117
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Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops
TLDR
A highly-digital clock multiplication architecture that achieves excellent jitter and mitigates supply noise in digital phase-locked loops (PLLs). Expand
  • 73
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A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy
TLDR
In this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. Expand
  • 132
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  • PDF
A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance
TLDR
A reference-less highly digital half-rate clock and data recovery (CDR) circuit with improved tolerance to input duty cycle error is presented. Expand
  • 45
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A Wide-Tracking Range Clock and Data Recovery Circuit
TLDR
A hybrid analog-digital quarter-rate clock and data recovery circuit (CDR) that achieves a wide tracking range and excellent frequency and phase tracking resolution is presented in this paper. Expand
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Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers
TLDR
The proposed PLL employs an averaging varactor based split-tuned LC-VCO and a servo loop which sets the charge-pump current to be inversely proportional to the square of oscillation frequency. Expand
  • 82
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A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity
TLDR
A self-referenced VCO-based temperature sensor with reduced supply sensitivity is presented. Expand
  • 55
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Analog Filter Design Using Ring Oscillator Integrators
TLDR
We propose applying ring oscillator integrators (ROIs) in the design of high order analog filters in a 90 nm CMOS process to validate the proposed techniques. Expand
  • 54
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Analysis of charge-pump phase-locked loops
TLDR
In this paper, we present an exact analysis for third-order charge-pump phase-locked loops using state equations. Expand
  • 172
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A 16-mW 78-dB SNDR 10-MHz BW CT $\Delta \Sigma$ ADC Using Residue-Cancelling VCO-Based Quantizer
TLDR
This paper presents a continuous-time (CT) ΔΣ modulator using a VCO-based internal quantizer. Expand
  • 103
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