Skip to search formSkip to main contentSkip to account menu

Power gating

Known as: Gating 
Power gating is a technique used in integrated circuit design to reduce power consumption, by shutting off the current to blocks of the circuit that… 
Wikipedia (opens in a new tab)

Related topics

Related topics

11 relations
CMOSClock gatingIddq testingIntegrated circuit

Broader (2)

Digital electronicsElectronic design automation

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline
Many crossbenchmarking results reported in the open literature raise optimistic expectations on the use of optical networks-on… 
Review
2013
Review
2013
Power management techniques for Wireless Sensor Networks: A review
During recent years, Wireless Sensor Networks captured the imagination of many researchers with number of applications growing… 
Highly Cited
2011
Highly Cited
2011
Power gating strategies on GPUs
As technology continues to shrink, reducing leakage is critical to achieving energy efficiency. Previous studies on low-power… 
2011
2011
AMD'S "LLANO" Fusion APU
2010
2010
NBTI-Aware Clustered Power Gating
The emergence of Negative Bias Temperature Instability (NBTI) as the most relevant source of reliability in sub-90nm technologies… 
2009
2009
Event-driven data and power management in high-density neural recording microsystems
We present design approaches and circuit techniques to perform data and power management in high-density neural recording… 
2008
2008
A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications
This work provides a dual-mode baseband transceiver chipset for wireless body area network (WBAN) system. The modulation schemes… 
2007
2007
Timing-driven row-based power gating
In this paper we focus on leakage reduction through automatic insertion of sleep transistors using a row-based granularity. In… 
2006
2006
Optimal simultaneous module and multivoltage assignment for low power
Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large… 
2005
2005
Power-Clock Gating in Adiabatic Logic Circuits
For static CMOS Clock-Gating is a well-known method to decrease dynamic losses. In order to reduce the static power consumption… 
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)