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Power gating

Known as: Gating 
Power gating is a technique used in integrated circuit design to reduce power consumption, by shutting off the current to blocks of the circuit that… 
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Related topics

Related topics

11 relations
CMOSClock gatingIddq testingIntegrated circuit

Broader (2)

Digital electronicsElectronic design automation

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Review
2013
Review
2013
Power management techniques for Wireless Sensor Networks: A review
During recent years, Wireless Sensor Networks captured the imagination of many researchers with number of applications growing… 
Highly Cited
2011
Highly Cited
2011
Power gating strategies on GPUs
As technology continues to shrink, reducing leakage is critical to achieving energy efficiency. Previous studies on low-power… 
2011
2011
A 190mV supply, 10MHz, 90nm CMOS, pipelined sub-threshold adder using variation-resilient circuit techniques
This paper presents a pipelined 32 bit sub-threshold adder in a 90nm CMOS technology that combines MHz-performance with sub-pJ… 
2011
2011
AMD'S "LLANO" Fusion APU
2010
2010
NBTI-Aware Clustered Power Gating
The emergence of Negative Bias Temperature Instability (NBTI) as the most relevant source of reliability in sub-90nm technologies… 
2009
2009
Design and application of multimodal power gating structures
Designing a power-gating structure with high performance in the active mode and low leakage and short wakeup time during standby… 
2009
2009
A Sub-$\mu$ s Wake-Up Time Power Gating Technique With Bypass Power Line for Rush Current Support
A sub-mus wake-up time power gating technique was developed for low-power SoCs. It uses two types of power switches and a… 
2008
2008
A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications
This work provides a dual-mode baseband transceiver chipset for wireless body area network (WBAN) system. The modulation schemes… 
2007
2007
Timing-driven row-based power gating
In this paper we focus on leakage reduction through automatic insertion of sleep transistors using a row-based granularity. In… 
2005
2005
Power-Clock Gating in Adiabatic Logic Circuits
For static CMOS Clock-Gating is a well-known method to decrease dynamic losses. In order to reduce the static power consumption… 
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