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Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs
Three-dimensional ICs provide a promising option to build high-performance compact SoCs by stacking one or more chips vertically. Through silicon vias (TSVs) form an integral component of the 3-D ICExpand
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Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies
SRAM cell read stability and write-ability are major concerns in nanometer CMOS technologies, due to the progressive increase in intra-die variability and Vdd scaling. This paper analyzes the readExpand
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Energy efficiency of the IEEE 802.15.4 standard in dense wireless microsensor networks: modeling and improvement perspectives
Wireless microsensor networks, which have been the topic of intensive research in recent years, are now emerging in industrial applications. An important milestone in this transition has been theExpand
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14.5 Envision: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable Convolutional Neural Network processor in 28nm FDSOI
ConvNets, or Convolutional Neural Networks (CNN), are state-of-the-art classification algorithms, achieving near-human performance in visual recognition [1]. New trends such as augmented realityExpand
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Design Issues and Considerations for Low-Cost 3-D TSV IC Technology
In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed.Expand
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Temperature dependent electrical characteristics of through-si-via (TSV) interconnections
In this paper, we investigate the electrical behavior of TSV with increasing temperatures (25–150°C). TSV capacitance, leakage current and TSV resistance with varying temperatures are reported. TSVExpand
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A/D Conversion Using Asynchronous Delta-Sigma Modulation and Time-to-Digital Conversion
An analog-to-digital conversion (ADC) scheme based on asynchronous ΔΣ modulation and time-to-digital conversion is presented. An asynchronous ΔΣ modulator translates the analog input to anExpand
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A 0.02mm2 65nm CMOS 30MHz BW all-digital differential VCO-based ADC with 64dB SNDR
A 300MHz all-digital differential VCO-based ADC occupies 0.02mm2 in 65nm CMOS, achieving a peak SFDR of 79dB and an SNDR of 64dB over a 30MHz BW. This high linearity is obtained using two VCOs inExpand
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A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication
A low-power impulse-radio ultra-wideband receiver is demonstrated for low data-rate applications. A topology selection study demonstrates that the quadrature analog correlation is a good receiverExpand
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Design issues and considerations for low-cost 3D TSV IC technology
3D TSV (through silicon via) technologies promise increased system integration at lower cost and reduced footprint [1]. Different variants of 3D technologies have recently been introduced inExpand
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