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Finite state machine with datapath
Known as:
FSMD
A Finite State Machine with Datapath (FSMD) is a mathematical abstraction that is sometimes used to design digital logic or computer programs. An…
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Related topics
Related topics
6 relations
Computer program
Datapath
Finite-state machine
Register-transfer level
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Broader (1)
Digital electronics
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
Power-aware through-silicon-via minimization by partitioning finite state machine with datapath
A. C. Abdullah
,
C. Y. Ooi
,
N. Ismail
,
Nurita Binti Mohammad
International Symposium on Circuits and Systems
2016
Corpus ID: 3092363
This paper proposes an extended Finite State Machine with Datapath (FSMD) partitioning that performs three-dimensional (3D) high…
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2010
2010
Finite State Machine with Datapath
P. Schaumont
2010
Corpus ID: 60482411
In this chapter, we introduce an important building block for efficient custom hardware design: the Finite State Machine with…
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2008
2008
Extracting Finite State Machine with Datapath models from the synthesized behavior in High Level Synthesis
D. Sarkar
,
C. Mandal
2008
Corpus ID: 15519945
High-Level Synthesis (HLS) comprises translating a behavioral specification into its corresponding Register Transfer Level (RTL…
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2008
2008
Automated formal verification of scheduling with speculative code motions
Youngsik Kim
,
N. Mansouri
ACM Great Lakes Symposium on VLSI
2008
Corpus ID: 15373483
We present a methodology for formal verification of scheduling phase of High-Level Synthesis (HLS) when speculative code motions…
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2006
2006
Executing Hardware as Parallel Software for Picoblaze Networks
Pengyuan Yu
,
P. Schaumont
International Conference on Field-Programmable…
2006
Corpus ID: 16133419
Multi-processor architectures have gained interest recently because of their ability to exploit programmable silicon parallelism…
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2006
2006
Nonuniform Synchronous Sampling Analog Interface
E. Saramov
,
M. Georgieva
Information Security Solutions Europe
2006
Corpus ID: 29046782
Traditional analog-to-digital conversion with uniform sampling is simple, but it adds to SoCs redundancy in its output data…
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2004
2004
FINITE STATE MACHINES WITH DATAPATH PARTITIONING FOR LOW POWER SYNTHESIS
A. Sudnitson
2004
Corpus ID: 17356481
Resent investigations have shown the very good results of digital systems and circuits optimization using integration of dynamic…
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2002
2002
Modeling a new RTL semantics in C++
S. Zhao
,
D. Gajski
IEEE International Symposium on Circuits and…
2002
Corpus ID: 206961091
In order to improve the productivity of current register transfer level (RTL) design practice, we argue that a new methodology of…
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2000
2000
Design of VHDL-based totally self-checking finite-state machine and data-path descriptions
C. Bolchini
,
R. Montandon
,
F. Salice
,
D. Sciuto
IEEE Transactions on Very Large Scale Integration…
2000
Corpus ID: 17247223
This paper presents a complete methodology to design a totally self-checking (TSC) sequential system based on the generic…
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1993
1993
A comparison of synchronous and asynchronous FSMD designs
R. Auletta
,
R. Reese
,
C. Traver
Proceedings of IEEE International Conference on…
1993
Corpus ID: 35707137
This paper presents a comparison of asynchronous and synchronous standard cell implementations for finite state machine with data…
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