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Datapath
Known as:
Internal datapath
A datapath is a collection of functional units, such as arithmetic logic units or multipliers, that perform data processing operations, registers…
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Related topics
Related topics
27 relations
1-bit architecture
64-bit computing
Arithmetic logic unit
Asynchronous system
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Review
2013
Review
2013
Applications of Multi-Terminal Memristive Devices: A Review
D. Sacchetto
,
P. Gaillardon
,
Michael Zervas
,
Sandro Carrara
,
G. Micheli
,
Yusuf Leblebici
IEEE Circuits and Systems Magazine
2013
Corpus ID: 14681793
Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic and…
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2011
2011
Synthesis and comparison of low-power high-throughput architectures for SAD calculation
Fabio Leandro Walter
,
C. Diniz
,
S. Bampi
Analog Integrated Circuits and Signal Processing
2011
Corpus ID: 9327584
Video applications are increasingly present in consumer electronic devices which require low-power and low-energy consumption…
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2009
2009
A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS
Himanshu Kaul
,
M. Anders
,
+4 authors
S. Borkar
IEEE Journal of Solid-State Circuits
2009
Corpus ID: 7505657
This paper describes a reconfigurable 4-way SIMD engine fabricated in 45 nm high-k/metal-gate CMOS, targeted for on-die…
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2008
2008
A coarse-grain reconfigurable architecture for multimedia applications featuring subword computation capabilities
C. Brunelli
,
F. Garzia
,
J. Nurmi
Journal of Real-Time Image Processing
2008
Corpus ID: 25962199
This paper presents the design and the implementation of a coarse-grain reconfigurable machine used as an accelerator for a…
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2006
2006
Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs
M. Hübner
,
C. Schuck
,
J. Becker
Proceedings 20th IEEE International Parallel…
2006
Corpus ID: 15827127
The development of field programmable gate arrays (FPGAs) had tremendous improvements in the last few years. They were extended…
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2006
2006
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
R. Dimond
,
O. Mencer
,
W. Luk
14th Annual IEEE Symposium on Field-Programmable…
2006
Corpus ID: 769703
In this paper, we investigate a combination of two techniques n struction coding and instruction re-ordering - for optimizing…
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Review
2002
Review
2002
Hardware-assisted fast routing
A. DeHon
,
Randy Huang
,
J. Wawrzynek
Proceedings. 10th Annual IEEE Symposium on Field…
2002
Corpus ID: 17709670
To fully realize the benefits of partial and rapid reconfiguration of field-programmable devices, we often need to dynamically…
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Highly Cited
2000
Highly Cited
2000
Effect of wire delay on the design of prefix adders in deep-submicron technology
Zhijun Huang
,
M. Ercegovac
Conference Record of the Thirty-Fourth Asilomar…
2000
Corpus ID: 14002321
This paper investigates the wire delay effect on the design of prefix adders when the technology moves from 250 nm to 70 nm. The…
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Review
1997
Review
1997
Embedded software in real-time signal processing systems: application and architecture trends
P. Paulin
,
C. Liem
,
M. Cornero
,
F. Naçabal
,
G. Goossens
Proceedings of the IEEE
1997
Corpus ID: 1171732
We present an extensive survey of trends in embedded processor use with an emphasis on emerging applications in wireless…
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1996
1996
High-performance computing using a reconfigurable accelerator
R. Hartenstein
,
J. Becker
,
R. Kress
,
H. Reinig
Concurrency Practice and Experience
1996
Corpus ID: 14613687
AbstractThis paper introduces the MoM-3 as a reconfigurable accelerator for high perform-ance computing at a moderate price. By…
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