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Register-transfer level
Known as:
RTL
, RTL design
, Register transfer level
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In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of…
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Related topics
Related topics
40 relations
Algorithmic state machine
Application checkpointing
Application-specific integrated circuit
Combinational logic
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
An FPGA implementation of OFDM transceiver for LTE applications
T. Pereira
,
M. Violas
,
J. Lourenco
,
A. Gameiro
,
Adão Silva
,
C. Ribeiro
2013
Corpus ID: 55070231
– The paper presents a real-time transceiver using an Orthogonal Frequency-Division Multiplexing (OFDM) signaling scheme. The…
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2006
2006
Statistical Power Estimation For Register Transfer Level
Y. A. Durrani
,
Teresa Riesgo
,
F. Machado
Proceedings of the International Conference Mixed…
2006
Corpus ID: 16320342
In this paper, we propose a macromodeling approach that allows to estimate the power dissipation of intellectual property (IP…
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2003
2003
From VHDL register transfer level to SystemC transaction level modeling: a comparative case study
Ney Laert Vilar Calazans
,
Edson I. Moreno
,
Fabiano Hessel
,
Vitor M. da Rosa
,
F. Moraes
,
E. Carara
16th Symposium on Integrated Circuits and Systems…
2003
Corpus ID: 16390809
Transaction level (TL) modeling is regarded today as the next step in the direction of complex integrated circuits and systems…
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2003
2003
MDA for SoC Design, Intensive Signal Processing Experiment
Pierre Boulet
,
J. Dekeyser
,
C. Dumoulin
,
P. Marquet
Forum on Specification and Design Languages
2003
Corpus ID: 6585448
The development of embedded applications is very difficult. Several different languages are usually used to specify different…
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2000
2000
Register-Transfer Level Simulation
T. Bräunl
IEEE/ACM International Symposium on Modeling…
2000
Corpus ID: 45336222
We present the tool Retro (Register-Transfer Object Hardware Simulator) for simulating digital hardware systems at register…
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1998
1998
Matisse: An Architectural Design Tool for Commodity ICs
Kayhan Küçükçakar
,
Chih-Tung Chen
,
J. Gong
,
Wim Philipsen
,
Thomas E. Tkacik
IEEE Design & Test of Computers
1998
Corpus ID: 13566713
To accelerate industrial adoption of behavioral synthesis, we have developed Matisse, an architectural design tool that increases…
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Highly Cited
1995
Highly Cited
1995
The Codesign of Embedded Systems: A Unified Hardware/Software Representation
Sanjaya Kumar
,
J. Aylor
,
Barry W. Johnson
,
W. Wulf
Springer US
1995
Corpus ID: 43052766
Current practice dictates the separation of the hardware and software development paths early in the design cycle. These paths…
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1993
1993
Sequential test generation and synthesis for testability at the register-transfer and logic levels
Abhijit Ghosh
,
S. Devadas
,
A. Newton
IEEE Trans. Comput. Aided Des. Integr. Circuits…
1993
Corpus ID: 45565062
The problem of test generation for nonscan sequential VLSI circuits is addressed. A novel method of test generation that…
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1989
1989
Synthesis from register-transfer level VHDL
J. Straus
Digest of Papers. COMPCON Spring 89. Thirty…
1989
Corpus ID: 31172270
A description is given of the use of VHDL (VHSIC hardware description language) as a register-transfer-level input language for…
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1985
1985
Verification of Register Transfer Level Parallel Control Sequences
V. Pitchumani
,
E. Stabler
IEEE transactions on computers
1985
Corpus ID: 19998198
This correspondence presents a method for proof of correctness of register transfer level (RTL) parallel control sequences that…
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