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Register-transfer level
Known as:
RTL
, RTL design
, Register transfer level
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In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of…
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Related topics
Related topics
40 relations
Algorithmic state machine
Application checkpointing
Application-specific integrated circuit
Combinational logic
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2010
2010
Illegal state extraction from Register Transfer Level
C. Hobeika
,
C. Thibeault
,
Jean-François Boland
Proceedings of the 8th IEEE International NEWCAS…
2010
Corpus ID: 35296456
In this paper we present a new automated tool for illegal state identification at Register Transfer Level (RTL). This tool is the…
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2008
2008
Variability-Tolerant Register-Transfer Level Synthesis
Anish Muttreja
,
S. Ravi
,
N. Jha
International Conference on VLSI Design
2008
Corpus ID: 10506013
Variability in circuit delay is a significant challenge in the design and synthesis of digital circuits. While the challenge is…
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Highly Cited
2006
Highly Cited
2006
Design for Testability
Laung-Terng Wang
,
X. Wen
,
Khader S. Abdel-Hafez
2006
Corpus ID: 60079306
2003
2003
MDA for SoC Design, Intensive Signal Processing Experiment
Pierre Boulet
,
J. Dekeyser
,
C. Dumoulin
,
P. Marquet
Forum on Specification and Design Languages
2003
Corpus ID: 6585448
The development of embedded applications is very difficult. Several different languages are usually used to specify different…
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2000
2000
Register-Transfer Level Simulation
T. Bräunl
IEEE/ACM International Symposium on Modeling…
2000
Corpus ID: 45336222
We present the tool Retro (Register-Transfer Object Hardware Simulator) for simulating digital hardware systems at register…
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1999
1999
Automatic insertion of gated clocks at register transfer level
N. Raghavan
,
V. Akella
,
Smita Bakshi
Proceedings Twelfth International Conference on…
1999
Corpus ID: 40697401
In synchronous circuits, the clock signal switches at every clock cycle and drives a large capacitance. As a result, the clock…
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Highly Cited
1997
Highly Cited
1997
Using a Programming Language for Digital System Design
Rajesh K. Gupta
,
S. Liao
IEEE Design & Test of Computers
1997
Corpus ID: 15486457
HDLs must satisfy important semantic requirements, especially when CAD tools are involved. Designers can meet these requirements…
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Highly Cited
1995
Highly Cited
1995
The Codesign of Embedded Systems: A Unified Hardware/Software Representation
Sanjaya Kumar
,
J. Aylor
,
Barry W. Johnson
,
W. Wulf
Springer US
1995
Corpus ID: 43052766
Current practice dictates the separation of the hardware and software development paths early in the design cycle. These paths…
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Highly Cited
1987
Highly Cited
1987
Design And Test of the 80386
P. Gelsinger
IEEE Design & Test of Computers
1987
Corpus ID: 25137913
A complex design effort, the 80386 was nevertheless one of the company's most successful projects. The work was completed in less…
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1978
1978
Register-Transfer Level Digital Design Automation: The Allocation Process
L. Hafer
,
A. C. Parker
Design Automation Conference
1978
Corpus ID: 13246253
This paper presents a portion of the register-transfer level computer aided design (RT-CAD) research at Carnegie-Mellon…
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