A detailed cycle-accurate interconnection network model (GARNET) is developed, inside the GEMS full-system simulation framework, that provides a detailed and accurate memory system timing model and shows that in improving on-chip network latency-throughput, EVCs do lead to better overall system runtime, however, the impact varies widely across applications.
This paper proposes a history-based DVS policy that judiciously adjusts link frequencies and voltages based on past utilization that realizes up to 6.3/spl times/ power savings and is accompanied by a moderate impact on performance.
This paper proposes express virtual channels (EVCs), a novel flow control mechanism which allows packets to virtually bypass intermediate routers along their path in a completely non-speculative fashion, thereby lowering the energy/delay towards that of a dedicated wire while simultaneously approaching ideal throughput with a practical design suitable for on-chip networks.
DeepInversion is introduced, a new method for synthesizing images from the image distribution used to train a deep neural network, which optimizes the input while regularizing the distribution of intermediate feature maps using information stored in the batch normalization layers of the teacher.
The algorithm uses the positive-polarity Reed-Muller expansion of a reversible function to synthesize the function as a network of Toffoli gates, and is able to quickly synthesize all four-variable and most five-variable reversible functions that were in the test suite.
This survey attempts to provide a comprehensive list of vulnerabilities and countermeasures against them on the edge-side layer of IoT, which consists of three levels: (i) edge nodes, (ii) communication, and (iii) edge computing.
This book is the most comprehensive introduction available to the range of techniques and tools used in digital testing, including fault simulation, CMOS testing, design for testability, and built-in self test.
This paper presents a comprehensive analysis of the energy requirements of the most popular transport-layer security protocol: Secure Sockets Layer (SSL), and investigates the impact of various parameters at the protocol level and the cryptographic algorithm level on the overall energy consumption for secure data transactions.
This paper presents a detailed design of the on-chip network router targeted at a 36-core shared-memory CMP system in 65nm technology, delivering a single-cycle no-load latency at 3.6GHz while achieving a peak switching data rate in excess of 4.6Tbits/s per router node.
The study shows that both passive attacks and active attacks can be successfully launched using public-domain information and widely available off-the-shelf hardware and proposed defenses against such attacks have the potential to mitigate the security risks associated with personal healthcare systems.