Anish Muttreja

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Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano-scale circuits. In this paper, it is observed that in spite of improved device characteristics, high active leakage may remain a problem for FinFET logic circuits. Leakage is found to contribute 31.3% of total power consumption in power-optimized FinFET logic(More)
Efficient energy and performance estimation of embedded software is a critical part of any system-level design flow. Macromodeling based estimation is an attempt to speed up estimation by exploiting reuse that is inherent in the design process. Macromodeling involves pre-characterizing reusable software components to construct high-level models, which(More)
Online monitoring of a physical phenomenon over a geographical area is a popular application of sensor networks. Networks representative of this class of applications are typically operated in one of two modes, viz. an always-on mode where every sensor reading is streamed to a base station, possibly after in-network aggregation, and a snapshot mode where a(More)
This paper proposes Silent Networking – a new method to significantly increase the lifetimes of energy-constrained nodes, networks, and mobile user devices. With Silent Networking, each network element powers off some or all of its radio interfaces during their naturally occurring silent periods, i.e., time periods when it does not expect to originate,(More)
Software energy estimation is a critical step in the design of energy-efficient embedded systems. Instruction-level simulation techniques, despite several advances, remain too slow for iterative use in system-level exploration. In this paper, we propose a methodology called <i>hybrid simulation</i>, which combines instruction set simulation with selective(More)
Software energy estimation is a critical step in the design of energy-efficient embedded systems. Instruction-level simulation techniques, despite several advances, remain too slow for iterative use in system-level exploration and for embedded systems with high software complexity. In this paper, we propose a methodology called hybrid simulation, which(More)
According to Moore's law, the number of transistors in a chip doubles every 18 months. The increased transistor-count leads to increased power density. Thus, in modern circuits, power efficiency is a central determinant of circuit efficiency. With scaling, leakage power accounts for an increasingly larger portion of the total power consumption in deep(More)
In modern circuits, power efficiency is a central determinant of circuit efficiency. The exponential increase in the number of transistors in a chip has led to increased chip power dissipation. Therefore, low-power circuits have become a top priority in modern VLSI design. With scaling, leakage power accounts for an increasingly larger portion (&#8811;40%)(More)