• Publications
  • Influence
A new algorithm for elimination of common subexpressions
TLDR
The problem of an efficient hardware implementation of multiplications with one or more constants is encountered in many different digital signal-processing areas, such as image processing or digital filter optimization, compiler optimization and many high-level synthesis tasks. Expand
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A Systematic Method to Evaluate and Compare the Performance of Physical Unclonable Functions
TLDR
We propose a systematic method to evaluate and compare the performance of physical unclonable functions (PUFs) using measured data from state-of-the-art FPGAs. Expand
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A large scale characterization of RO-PUF
TLDR
We characterize a PUF based on ring oscillator (RO) using a significantly large population of 125 FPGAs. Expand
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Improving the quality of a Physical Unclonable Function using configurable Ring Oscillators
  • A. Maiti, P. Schaumont
  • Computer Science
  • International Conference on Field Programmable…
  • 29 September 2009
TLDR
A Ring Oscillator based PUF is a promising solution for FPGA platforms. Expand
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AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks
TLDR
This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18- m$CMOS consisting of an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching engine, template storage, and an interface unit. Expand
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Secure FPGA circuits using controlled placement and routing
TLDR
We show that the direct mapping of a secure ASIC circuit-style in an FPGA does not preserve the same level of security, unless our symmetrical routing technique is employed. Expand
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Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment
TLDR
We present a secure coprocessor that does not leak information through the power supply, which is a major and easy- access side-channel leakage source. Expand
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Offline Hardware/Software Authentication for Reconfigurable Platforms
TLDR
We describe an offline authentication scheme for IP modules and the hardware platform, and enable us to provide authentication and integrity assurances to both the system developer and IP provider. Expand
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Formal Verification of Software Countermeasures against Side-Channel Attacks
TLDR
We propose the first SMT-solver-based method for formally verifying the security of a masking countermeasure against side-channel attacks using a series of quantifier-free first-order logic formulas, whose satisfiability can be decided by an off-shelf SMT solver. Expand
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Design and performance testing of a 2.29-GB/s Rijndael processor
TLDR
This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput at 56 mW of power consumption in a 0.18-spl mu/m CMOS standard cell technology. Expand
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