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Cryphonectria parasitica vegetative compatibility type analysis of populations in south-western France and northern Spain.
A comprehensive study of the population biology of Cryphonectria parasitica, the causal agent of chestnut blight, is required to understand the spread of the epidemic in Europe and its naturalExpand
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Human granulocytic ehrlichiosis: report of a case in Northern California.
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Early evaluation for performance enhancement in phased logic
Data-dependent completion time is a well-known advantage of self-timed circuits, one that allows them to operate at average rather than worst-case execution rates. A technique called early evaluationExpand
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Generalized early evaluation in self-timed circuits
Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have been applied toExpand
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Rapid-prototyping of high-assurance systems
  • R. Auletta, C. Traver
  • Computer Science
  • [] Proceedings Third Great Lakes Symposium on…
  • 5 March 1993
The rapid prototyping of VLSI systems from an abstract specification is described. The high-assurance rapid-prototyping environment HARP is used. HARP is based on the translation of an abstractExpand
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Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion
A technique for automatic insertion of slack matching buffers for performance enhancement in the asynchronous design style known as Phased Logic (PL) is described. A description of how slack matchingExpand
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The multidisciplinary international virtual design studio (MIVDS)
The International Virtual Design Studio (MIVDS) that was originated between the Departments of Mechanical Engineering of Union College (UC) and the Middle East Technical University (METU) is nowExpand
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Cell designs for self-timed FPGAs
A self-timed programmable architecture used for the implementation of Phased Logic (PL) systems is described. PL systems are automatically translated from clocked designs and result in self-timedExpand
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Arithmetic logic circuits using self-timed bit level dataflow and early evaluation
A logic style known as Phased Logic (PL) is applied to arithmetic circuits. Phased logic is a dual-rail LEDR logic style that allows automatic translation from a clocked netlist to a self-timedExpand
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A fine-grain Phased Logic CPU
A five-stage pipelined CPU based on the MIPs ISA is mapped to a self-timed logic family known as Phased Logic (PL). The mapping is performed automatically from a netlist of D-Flip-Flops and 4-inputExpand
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