Skip to search formSkip to main contentSkip to account menu

CAS latency

Known as: CAS, Memory access time, CL 
Column Access Strobe (CAS) latency, or CL, is the delay time between the moment a memory controller tells the memory module to access a particular… 
Wikipedia (opens in a new tab)

Related topics

Related topics

18 relations
AMD 10hComputer data storageDouble data rateDynamic random-access memory

Broader (1)

Computer memory

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2013
Highly Cited
2013
Worst Case Analysis of DRAM Latency in Multi-requestor Systems
As multi-core systems are becoming more popular in real-time embedded systems, strict timing requirements for accessing shared… 
2013
2013
Performance Evaluation of NAS Parallel Benchmarks on Intel Xeon Phi
NAS parallel benchmarks (NPB) are a set of applications commonly used to evaluate parallel systems. We use the NPB-OpenMP version… 
2012
2012
Multithreaded FPGA acceleration of DNA sequence mapping
In bioinformatics, short read alignment is a computationally intensive operation that involves matching millions of short strings… 
2011
2011
Energy efficient Phase Change Memory based main memory for future high performance systems
Phase Change Memory (PCM) has recently attracted a lot of attention as a scalable alternative to DRAM for main memory systems. As… 
2005
2005
Data space-oriented tiling for enhancing locality
Improving locality of data references is becoming increasingly important due to increasing gap between processor cycle times and… 
Highly Cited
1999
Highly Cited
1999
Performance estimation of embedded software with instruction cache modeling
Embedded systems generally interact in some way with the outside world. This may involve measuring sensors and controlling… 
Highly Cited
1995
Highly Cited
1995
Control flow prediction with tree-like subgraphs for superscalar processors
In order to fetch a large number of instructions per cycle, wide-issue superscalar processors have to predict the outcome of… 
Highly Cited
1991
Highly Cited
1991
A unified systolic array for discrete cosine and sine transforms
A linear systolic array for the discrete cosine transform, discrete sine transform, and their inverses is developed. It generates… 
Review
1988
Review
1988
The Horizon supercomputing system: architecture and software
An overview is given of Horizon, a shared-memory multiple-instruction-stream-multiple-data-stream computer architecture currently… 
Review
1987
Review
1987
Incorporating Data Flow Ideas into von Neumann Processors for Parallel Execution
The issues of memory latency, synchronization, and distribution costs in multiprocessors are reviewed. The approaches taken by… 
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)