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CAS latency
Known as:
CAS
, Memory access time
, CL
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Column Access Strobe (CAS) latency, or CL, is the delay time between the moment a memory controller tells the memory module to access a particular…
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Related topics
Related topics
18 relations
AMD 10h
Computer data storage
Double data rate
Dynamic random-access memory
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Broader (1)
Computer memory
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
Performance Evaluation of NAS Parallel Benchmarks on Intel Xeon Phi
Arunmoezhi Ramachandran
,
Jérôme Vienne
,
R. V. D. Wijngaart
,
L. Koesterke
,
I. Sharapov
International Conference on Parallel Processing
2013
Corpus ID: 10095454
NAS parallel benchmarks (NPB) are a set of applications commonly used to evaluate parallel systems. We use the NPB-OpenMP version…
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2011
2011
Designing fast architecture-sensitive tree search on modern multicore/many-core processors
Changkyu Kim
,
J. Chhugani
,
+6 authors
P. Dubey
TODS
2011
Corpus ID: 8400514
In-memory tree structured index search is a fundamental database operation. Modern processors provide tremendous computing power…
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2009
2009
Application Exploration for 3-D Integrated Circuits: TCAM, FIFO, and FFT Case Studies
W. R. Davis
,
Eun Chu Oh
,
A. Sule
,
P. Franzon
IEEE Transactions on Very Large Scale Integration…
2009
Corpus ID: 15108369
3-D stacking and integration can provide system advantages. This paper explores application drivers and computer-aided design…
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2006
2006
Memory latency consideration for load sharing on heterogeneous network of workstations
A. Akkas
,
M. Schulte
2006
Corpus ID: 195714641
2005
2005
Data space-oriented tiling for enhancing locality
I. Kadayif
,
M. Kandemir
TECS
2005
Corpus ID: 7155430
Improving locality of data references is becoming increasingly important due to increasing gap between processor cycle times and…
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1998
1998
Evaluation of Existing Architectures in IRAM Systems
Ngeci Bowman
,
Neal Cardwell
,
Christos Kozyrakis
,
C. Romer
,
Helen J. Wang
1998
Corpus ID: 18368682
Computer memory systems are increasingly a bottleneck limiting application performance. IRAM architectures, which integrate a CPU…
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1993
1993
Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips
Tom Chen
,
G. Sunada
IEEE Transactions on Very Large Scale Integration…
1993
Corpus ID: 35948898
A memory architecture with the capability of self-testing and self-repairing is presented. The contributions of this memory…
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Highly Cited
1991
Highly Cited
1991
A unified systolic array for discrete cosine and sine transforms
Long-Wen Chang
,
Ming-Chang Wu
IEEE Transactions on Signal Processing
1991
Corpus ID: 206468006
A linear systolic array for the discrete cosine transform, discrete sine transform, and their inverses is developed. It generates…
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1980
1980
Circuit Implementation of Fusible Redundant Addresses on RAMs for Productivity Enhancement
B. Fitzgerald
,
E. Thoma
IBM Journal of Research and Development
1980
Corpus ID: 59596780
This paper describes the circuit schemes used to substitute redundant storage locations for defective ones found during testing…
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1967
1967
Considerations in block-oriented systems design
Donald H. Gibson
AFIPS '67 (Spring)
1967
Corpus ID: 15316786
The feasibility of transmitting blocks of words between memory and CPU is the subject of this study. The question is pertinent to…
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