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CAS latency
Known as:
CAS
, Memory access time
, CL
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Column Access Strobe (CAS) latency, or CL, is the delay time between the moment a memory controller tells the memory module to access a particular…
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Related topics
Related topics
18 relations
AMD 10h
Computer data storage
Double data rate
Dynamic random-access memory
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Broader (1)
Computer memory
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors
J. Hu
,
Qingfeng Zhuge
,
C. Xue
,
Wei-Che Tseng
,
E. Sha
ACM Transactions on Embedded Computing Systems
2014
Corpus ID: 13920796
The recent emergence of various Non-Volatile Memories (NVMs), with many attractive characteristics such as low leakage power and…
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2000
2000
Efficient ECC-Based Directory Implementations for Scalable Multiprocessors
K. Gharachorloo
,
L. Barroso
,
A. Nowatzyk
2000
Corpus ID: 18947352
With increasing chip densities, next-generation microprocessor designs have the opportunity to integrate many of the traditional…
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1997
1997
The hierarchical multi-bank DRAM: a high-performance architecture for memory integrated with processors
T. Yamauchi
,
Lance Hammond
,
K. Olukotun
Proceedings Seventeenth Conference on Advanced…
1997
Corpus ID: 1090759
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory…
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Review
1997
Review
1997
Design of the 21174 Memory Controller for DIGITAL Personal Workstations
R. Schumann
Digital technical journal of Digital Equipment…
1997
Corpus ID: 39438234
Vol. 9 No. 2 1997 57 As microprocessor performance has relentlessly improved in recent years, it has become increasingly…
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1996
1996
The Performance Implications of Locality Information Usage in Shared-Memory . . .
1996
Corpus ID: 14788796
caches used in scalable shared-memory architectures can avoid high memory access time only if data is referenced within the…
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1996
1996
UltraSPARC-II: the advancement of ultracomputing
G. Goldman
,
P. Tirumalai
COMPCON '96. Technologies for the Information…
1996
Corpus ID: 2919912
UltraSPARC-II extends the family of Sun's 64-bit SPARC V9 microprocessors, building on the UltraSPARC-I pipeline and adding…
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1995
1995
Conflict-Free Access for Streams in Multimodule Memories
M. Valero
,
T. Lang
,
Montse Peiron
,
E. Ayguadé
IEEE Trans. Computers
1995
Corpus ID: 2059273
Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free access…
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1994
1994
Using virtual lines to enhance locality exploitation
O. Temam
,
Y. Jégou
International Conference on Supercomputing
1994
Corpus ID: 14291919
Because the spatial locality of numerical codes is significant, the potential for performance improvements is important. However…
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1992
1992
Compilation-based prefetching for memory latency tolerance
C. Selvidge
1992
Corpus ID: 13230995
Program locality is typically considered at a macroscopic level corresponding to aggregate program behavior. We investigate…
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1992
1992
Memory Latency Effects in Decoupled Architectures with a Single Data Memory Module
L. John
,
P. T. Hulina
,
L. Coraor
[] Proceedings the 19th Annual International…
1992
Corpus ID: 9500710
Decoupled computer architectures partition the memory access and execute functions in a computer program and achieve high…
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